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LMK05318B: APLL1 divider change

Part Number: LMK05318B
Other Parts Discussed in Thread: LMK5C33216, LMK5B33216

Tool/software:

Hi TI, 

We'd like to use the APLL1 of the LMK05318B in free-running mode and apply small frequency deviations for fine tuning the frequency (similar to the DCO FDEV functionality of the DPLL, but without requiring an external reference for locking). The "Register Programming Manual" (https://www.ti.com/lit/ug/snau254a/snau254a.pdf) contains two register maps, one on page 1 and one on page 79. The second half of the PDF (p.79+) describes a PLL1_FDEV functionality in R116-R122 which might act similar to the DCO_FDEV, but we weren't able to see a change in the APLL1 frequency when using those registers. Did we miss some hidden feature that needs to be activated for APLL1 tuning? Furthermore, the first half of the PDF does not list the PLL1_FDEV registers (= reserved) and they are not mentioned in the datasheet. Thanks for your support.

Br, PF

  • Hi PF,

    The register programming manual is pending update and correction to combine the two tables.

    The LMK05318B does not support an APLL DCO (only the DPLL DCO). Our newer parts such as the LMK5B33216 and LMK5C33216 have both DPLL and APLL DCOs.

    We have had previous customers route an LMK05318B output to the PRIREF/SECREF input to force the DPLL on. Doing so, allows the DPLL to stay enabled which provides the access to the DPLL DCO.

    Regards,

    Jennifer

  • HI Jennifer, 

    thanks for the feedback, that answers in principle my question, but one last thing.

    Do you expect a difference if we feed in the APLL1 output to PRIREF compared to feeding in the external TCXO into XO input AND PRIREF input?

    Br, PF

  • Hi PF,

    Feeding the TCXO input into the PRIREF input is another option and I don't expect much difference. You may consider using an output instead of the TCXO input for layout/routing purposes.

    Regards,

    Jennifer