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CDCE913 not locking, what am I doing wrong?

Cypher Punks
Intellectual 410 points
Other Parts Discussed in Thread: CLOCKPROTo be precise, the output frequency is about 5% high (and fluctuates a lot) and there's so much jitter that 5 cycles after the trigger point the scope screen is a confused mess of up- and down-edges.

Obviously, some pilot error is involved, but I've been RTFMing for a while with no joy.

The input is a 19.2 MHz oscillator. Configuring Y1 to pass through the input shows a good waveform. (The edges stay in place on the scope screen even milliseconds after the trigger.)

The PLL is configured for M = 3, N = 16, Pdiv = 25. This should run the VCO at 102.4 MHz and produce an output of 4.096 MHz.

The derived PLL parameters are P = 2, Q = ⌊2P·N/M⌋ = 21, R = 2P·N mod M = 1.

The configuration I'm using is:

  • Registers 0x10–0x12 = 0 (no SSC)
  • Register 0x13 = 0 (always use PLL1 configuration 0)
  • Register 0x14 = 0x6f (Y2 = PLL1/Pdiv2, PLL1 enabled, Y2 enabled)
  • Register 0x15 = 0 (always use Y2 configuration 0)
  • Register 0x16 = 0x19 (Pdiv2 = 25)
  • Register 0x18 = 0x01 (N = 16)
  • Register 0x19 = 0x00 (R = 1)
  • Register 0x1a = 0x02 (Q = 21 = 0x15)
  • Register 0x1b = 0x08 (P = 2, 80 ≤ FVCO
I also tried N = 32, fVCO = 204.8 MHz, Pdiv = 50, with no obvious striking improvement.

However, the output makes me suspect the PLL is not locked. Output frequency is about 4200 kHz with a lot of wander. The 1.8V supply looks good (1.805 V, dedicated LDO, decoupled with 0.1 μ ∥ 0.1 μ ∥ 1 μ ∥ 100 μF (tant)). Any idea what I might be doing wrong? ′

  • 0
    Intellectual 410 points
    Just a follow-up: I checked that the ClockPro software calculated the same register contents as I did. While using it, I noticed that it tended to add common factors to M/N to make the numbers as large as possible. (At the register level, this amounts to scaling M and R by the same value.)

    I tried its suggestions of 2720/510 (to make 102.4 MHz) and 4064/381 (to make 204.8 MHz). Symptoms not obviously changed.

    Is this just a quirk of the ClockPro software, or does multiplying M and N by some common value K make any difference to the PLL output?

    Another interesting question is whether using a larger value P than necessary makes a difference. Rather than P=2, Q=21, R=1, I could choose P=3, Q = 42, R = 2. Is there any advantage or disadvantage to choosing Q in the 32–63 range rather than 16–31?

    Thank you!

  • 0
    Intellectual 410 points
    D'oh. False alarm. The input clock is not clean; I'm getting some noise on the input clock causing false edges, and runt cycles. Which is driving the PLL nuts. A bit of playing with scope trigger conditions found the short cycles in the PLL-bypass clocks.

    Actually tracking down this problem is going to be great fun; it's up at frequencies where probe technique is not negotiable. Whee.

  • 0 in reply to Cypher Punks
    Intellectual 410 points
    It was the grounding. Due to a layout error, the clock signal path wasn't over a solid plane. Caused all sorts of noise. Cleaned it up and all is solid.

    Sorry for the false alarm.