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LMK5C33216: delay variation between two SYSREF

Part Number: LMK5C33216

Tool/software:

We are integrating on the LMK5C33216 and are having some trouble understanding the intent of the datasheet.  We are trying to synchronize the counters of two SYSREF outputs as described in page 57 and 58 of the datasheet.  We are using the SYNC_SW via R21[6] vs the hardware GPIO.   We initially tried the following sequence:

 

  1. Write all setup registers except SYNC_SW.
  2. Assert SYNC_SW.
  3. De-assert SYNC_SW.

 

The resulting behavior was that the SYSREF outputs seemed to be turned off.

 

We tried a 2nd sequence as follows:

 

  1. Assert SYNC_SW.
  2. Write all setup registers except SYNC_SW.
  3. De-assert SYNC_SW.

The result of this sequence was that both outputs came up and seemed to have the rising edge somewhat synchronized, but the the time delay between the rising edges of the outputs seemed to vary on the order of a few nanoseconds between sequential trials of the 2nd sequence described above.  

 

Our goal is to have picoseconds of variation in the delay between multiple sequential trials of a control sequence.  Is there any insight on the order of register writes(using SYCNC_SW) that would result in the minimum delay variation between two SYSREF outputs after running the suggested control sequence multiple times?  

 

I created the graphic below to help illustrate the goal of the sequence.