LMH1983: LMH1983 PLL4 at 48MHz

Jerry Hodges

Part Number: LMH1983

Tool/software:

I want to generate 48MHz clock on PLL4 with 27MHz input from PLL1. Is PLL4 capable of being setup to operate at 48MHz?

I've reviewed AN2108 example to generate 44.1KHz but the values that were calculated and presented in the paper do not actually generate 44.1KHz. Is there an error in that paper?

2 months ago

0 Noel Fung 2 months ago

TI__Guru* 90680 points

Hi Jerry,

We can set PLL4_DIV to get 48kHz.

0 Jerry Hodges 2 months ago

Prodigy 10 points

Hi Noel,

I made a typo. I'm trying to generate 48MHz. I did try by changing PLL4_DIV to be 1 so the out put is 98.304MHz/2 = 49.152MHz (verified by measurement). I then tried to tune VCO Range to achieve 48MHz but the resolution was too course and also at the settings that appear to get close to 48MHz the PLL4 Lock is not stable indicating possible instability.

VCO RNG = 0x1E, PLL4_Out = 48.304MHz

VCO RNG = 0x1F, PLL4_Out = 47.87MHz

+1 Noel Fung 2 months ago in reply to Jerry Hodges

TI__Guru* 90680 points

Hi Jerry,

From PLL4 block diagram, we can derive two equations.

27MHz / R = VCO / N / 8 - eq#1

VCO / 3 / IS125M / 2^PLL4_DIV = fout - eq#2

Given fout = 48MHz and VCO = 1.3GHz to 1.69GHz
re-arrange eq#2
VCO = fout x 3 x IS125M * 2^PLL4_DIV
try IS125M = 4
VCO = 48M x 3 x 4 x 2^PLL4_DIV
= 576M x 2^PLL4_DIV
= no solution
try IS125M = 5
VCO = 48M x 3 x 5 x 2^PLL4_DIV
= 720M x 2^PLL4_DIV
if PLL4_DIV = 1
VCO = 720M x 2
= 1440MHz

Since the chip is design to have default 27M / 75 = 360kHz,
try R = 75
use eq#1 to find N
360k = 1440M / N / 8
N = 500

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LMH1983: LMH1983 PLL4 at 48MHz