LMK04828: Muti-board LMK clock

JINGDA LIU

Part Number: LMK04828

Tool/software:

Hi experts,

I still have some questions about synchronizing multiple LMK devices. When I tested the 500MHz output from the LMKs on two clock boards, I noticed some jitter between on them, which also affected the LMX output.

My current configuration is based on the 2b case (dual loop nested ZDM) as shown in the diagram. I think that with ZDM, the 500MHz edge output should align with the edges of the 5MHz input. If both 5MHz edges are aligned, then both 500MHz edges should be aligned. I am currently using clkin0 as the 5MHz reference input, so do I still need to send a sync pulse to the sync pin to reset the divider? Could you point me in the right direction?

Thank you!

LMK04828 CLOCK FILE:

MTS_5M_AutoRef_5M_SYSREF_250M_Clocks_0Delay_Nested_SYNC_new.tcs

Refer: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1361403/lmk04828-multi-board-rfsoc/5205499?tisearch=e2e-sitesearch&keymatch=RFSOC#5205499

Regards,

Jingda

4 months ago

0 William Pfennigwerth 4 months ago

TI__Expert 8231 points

Jingda,

I will get back to you tomorrow.

Regards,

Will

0 William Pfennigwerth 4 months ago in reply to William Pfennigwerth

TI__Expert 8231 points

Jingda,

Which of your outputs are misaligned? Outputs from the same board or outputs from different boards?

I believe you will still have to send a synch pulse to reset the output dividers.

Regards,

Will

0 JINGDA LIU 4 months ago

Prodigy 20 points

Hi Will,

Thanks for your response!

The DCLKout0 from the LMK of the two boards is not aligned. Additionally, I have measured Clk_in0 and DCLKout0 on a single board, and there is also phase jitter. Could this be an issue with my clock file?

Could I achieve multi-board synchronization if I only use the dual-loop ZDM mode without synch pulse?

Regards,

Jingda

+1 William Pfennigwerth 4 months ago in reply to JINGDA LIU

TI__Expert 8231 points

Jingda,

Case 2a/b is provides that the sysref outputs will be aligned without a SYNC. It also provides that all clock outputs can be aligned with a SYNC that can be done at anytime as opposed to strict SYNC timing requirements in other cases. So you can either send hardware or software sync signal to reset the output dividers and align the outputs, or you could even use the SYNC_PLLY_DLD to trigger an automatic SYNC pulse when the the PLLs are locked.

Regards,

Will

0 JINGDA LIU 4 months ago in reply to William Pfennigwerth

Prodigy 20 points

Hi will,

Thank you for your response, I now have a clearer understanding, and I will give it a try

Clock & timing

Clock & timing forum

LMK04828: Muti-board LMK clock