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LMK05318B: Generating 156.25 MHz synchonized to PPS

daloti
Prodigy 10 points
Part Number: LMK05318B

Tool/software:

II was wondering if you had any advice on generating a 156.25 MHz signal synchronized to a PPS signal using the LMK06318B (or another part if one is better suited). I have available as inputs the PPS signal and a configurable higher-frequency signal up to 62.5 MHz that is synchronized to the PPS. The high frequency signal has the limitation that period has to be an even number of nanoseconds that is 16 ns or greater.

One option is to use the configurable high frequency signal as XO input and multiply it up to 156.25 MHz. Set it to, for instance, 31.25 Mhz and multiply it by 5.This just uses the APLL.

Another option, and probably more typical for this chip, is to use the PPS as reference input for the DPLL, use the synchronized high frequency signal as XO, and generate the 156.25 Mhz signal using APLL1. I see it would also be possible to generate a PPS output signal using zero-delay mode.

Any advice on the relative merits of these 2 approaches? The degree to which the 156.25 MHz signal is synchronized to the PPS is the important criterion. 

  • 0
    TI__Expert 3135 points

    Hi Daloti,

    LMK05318B can operate in APLL-only mode or DPLL mode as you described. A few things to highlight between these modes to help you choose a suitable operation for your system:

    - In APLL-only mode: XO is used as the reference for APLL, output is synced to the XO

    - In DPLL mode: XO provides reference to APLL. When PPS input signal to DPLL reference becomes valid, the device will lock to DPLL input. This provides long-term stability to the system that if XO has some ppm errors, the device will adjust to stay inlock with DPLL reference. When PPS signal is lost, the device enters holdover referencing XO's error. Once PPS signal is back, device exits holdover and stay in lock with DPLL reference.

    Since the configurable higher-frequency signal is already synchronized to PPS signal, I see no problem using either mode. However, DPLL would provide some advantages over APLL-only mode such as long-term stability as described above and also DPLL loop bandwidth is much narrower than APLL LBW so it would help filter out noises in the input signals.

    Also, LMK05318B can do open-loop zero-delay mode through DPLL phase offset register control (DPLL_REF_SYNC_PH_OFFSET bits).

    Note that DPLL reference can take much lower frequency signal than XO frequency range.

    -Riley