LMX2820: Phase noise degredation

Hi Nir,

Try again with the following sequence, if it is different from your programming sequence.

Initialization register setting
1. Set DBLBUF_PLL_EN, DBLBUF_CHDIV_EN, DBLBUF_OUTBUF_EN, DBLBUF_OUTMUX_EN = 1
2. Set DBLR_CAL_EN = 0; INSTCAL_SKIP_ACAL = 0
3. If VCO doubler is required, set INSTCAL_DBLR_EN = 1, otherwise set this bit to 0
4. Set INSTCAL_DLY = T x fosc (in MHz) / 2^CAL_CLK_DIV, where T = 2.5 x CBIASVCO / 0.47µF. CBIASVCO is the bypass capacitor at pin 3
5. Configure other registers to lock to 5.65GHz without any calibration assist
6. Set INSTCAL_PLL_NUM = 2^32 x (PLL_NUM / PLL_DEN)
Programming
7. Vcc power up LMX2820
8. Program all the registers, LMX2820 should lock to 5.65GHz
InstCal calibration
9. Program INSTCAL_EN = 1
9.5 run Index routine
10. Program R0 (with FCAL = 1), calibration will begin
11. Wait 100ms
12. Program R0 (with FCAL = 0) to complete the calibration
13. If LD pin did not turn HIGH, program RESET = 1 to reset LMX2820. After LMX2820 is reset, repeat Step 8 to 12
Changing VCO frequency
14. Program INSTCAL_PLL_NUM, PLL_N, PLL_NUM and PLL_DEN (if their value have change)
15. Program R0 (with FCAL = 0) to change VCO frequency

9.5 Index routine
1. Program R106[10] = 1 (0X6A 0400)
2. Program R107[5:0] = 0 (0x6B 0000)
3. Program R108 = 0 (0x6C 0000)
4. Program R109 = 0 (0x6D 0000)
5. Program R106[9:0] = 514 (0x6A 0602)
6. Program R106[11] = 1 (0x6A 0E02)
7. Program R106[11] = 0 (0x6A 0602)
8. Repeat step 5 to 7 for R106[9:0] = 515 to 519
9. Program R106[10] = 0 (0x6A 0000)

Hi

I'm doing exactly what you wrote, except section 9.5

Can you elaborate? What are these registers and why they are important for the calibration process?

Do you thing it's somehow related to my problem?

Is it important to program all registers (section 1 to 12) in this exact order?

OK so I have added section 9.5, but still, the phase noise is changing and degredating between frequencies.

The frequency is locking in all of my bandwidth (with Fcal = 0),  that means that the calibration was successful, right?

Hi Nir,

Could you provide your configuration, I can try this out in the lab.

At what frequency the phase noise change significantly?

Hi Noel

At 7GHz, with small steps of 10MHz

This is the loop filter:

https://i.postimg.cc/2SQ6mhTd/loop-filter.png

I see the problem with internal dividers and also when using external mixer

On this thread i wrote the programming sequence (I have added the 9.5 section):

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1398185/lmx2820-lmx2802---improve-lock-time/5352972#5352972

I can send you some photos on private.

Thank you,

Nir

Hi Nir,

I need more information on your application. Do you know who is your TI local support team contact?

Hi

I wrote our TI local support team, they sent you an email

Thanks