Tool/software:
The datasheet (p.8) said:
"The LVCMOS driver supports full rail-to-rail swing when VDDO_x is 1.8 V ±5%. When VDDO_x is 2.5 V or 3.3 V, the LVCMOS driver will not fully swing to the positive rail due to the dropout voltage of the output channel's internal LDO regulator."
As what it said, can i apply a 3.3V on VDDO in order to get a larger swing range of LVCMOS? or it may damage the chip?
Our customer required 1.4Vpp at least, meanwhile the minimal VOH of LMK05318 for LVCMOS18 is 1.2v, maxium VOL for LVCMOS18 is 0.4V. So in worst case, the output cannot satisfied requirement.
If the answer is we cannot apply 3.3V on it, dose Ti have any solution to get the clock output a larger swing?
