Tool/software:
Hi,
Could you check attached TCS file?
With this tcs, Clock_out0,2 is ok but there is no output at Clock_out1.
Please check what parameter has to be modified.
Fist_LMK04832_config_240905.tcs
Thanks.
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Tool/software:
Hi,
Could you check attached TCS file?
With this tcs, Clock_out0,2 is ok but there is no output at Clock_out1.
Please check what parameter has to be modified.
Fist_LMK04832_config_240905.tcs
Thanks.
Hi David,
I see that the device clk is configured as a SYSREF output.
In order to generate SYSREF outputs you must first SYNC the device and then follow the instructions to enable SYSREF found on page 31 of DS.
Regards,
Vicente
Hi Vicente,
Thanks for your support.
Secondary PLL setting is abnormal.
Could you check TCS file?
Second_LMK04832_config_240909.tcs
below is the schematic.
Thanks.
Hello.
My name is Kyubok,Lee and I work at SolidWintech.
I would like to inquire about PLL(LMK04832) settings.
The PLL2 block is being set using the TICS-PRO program.
I wrote Raw Registers as an attached file, but it is still not locked. Of course, TICS-Program shows that PLL-1 and PLL-2 are locked.
Is it possible to check if the attached file is normal?
Thanks.
Second_LMK04832_config_240910-t.tcs
Hello all,
I have created a new configuration file that should result in the satisfactory operation of both PLLs (it is a double-loop configuration, please let me know if that is not what you desired). It is based on the schematic, but I do have a few concerns that need to be addressed.
I am not sure what you are doing with your SYNC and RESET pins. The previous config had the SYNC pin disabled, but the schematic has it connected to an input. Your schematic had a SYSREF output, which would require the SYNC pin being enabled to be driven (in my config file, I set the SYNC mode to be continuous, meaning you will see *some* output on CLK_OUT1, change based on your need). The RESET pin is pulled high with a low resistor value, which will result in RESET being high for the entirety of operation, which will render the entire buffer useless. Please consult the data sheet, specifically 8.6.2.5 RESET_MUX, RESET_TYPE, for more information.
Finally, all of your outputs on the schematic are set up for LVPECL output mode, but your configuration file sets all outputs as LVDS. That difference should be rectified.
Please let me know if you have any further questions.
Thanks,
Michael