LMK5B33216: Sync Issue

Raja Venkateshwaran

Part Number: LMK5B33216

Tool/software:

We are unable to sync pps with external pps settings we believe that the dpll is not locked because we lack access to recommended version of mat lab (2015b).Also I have attached the .tcs file.

3 months ago

0 Jennifer Bernal 3 months ago

TI__Genius 11965 points

Hi Raja,

Are you unable to download the Matlab version from this link? https://www.mathworks.com/products/compiler/matlab-runtime.html

The runtime is necessary for DPLL loop filter calculations which impact DPLL lock.

Regards,

Jennifer

0 Rishi Nandha Vanchinathan 3 months ago in reply to Jennifer Bernal

Prodigy 40 points

Hi Jennifer, we were able to run the runtime. Thanks. We are still not able to get our DPLL lock to our PPS input. I'm attaching our TICS Pro file for reference 24sep_nozdm.tcs

We are reading back 0x32 to check if our REF1 is clearing the validation checks. We are reading back 02 indicating that it is indeed clearing it. Then we read back 0x22 and 0x24, we are getting 0xD1 and 0xC0 respectively. This seems to indicate that DPLLs have lost lock. And that DPLL1 is in holdover either after somehow acquiring lock in between and DPLL2 hasnt acquired lock for the first time yet

We have tried both a small LBW of 10mHz and a large LBW of 20Hz and are not able to configure the DPLLs to lock to the Input PPS.

Can you please suggest changes in the configuration to achieve a reliable lock?

0 Jennifer Bernal 3 months ago in reply to Rishi Nandha Vanchinathan

TI__Genius 11965 points

Hi Rishi,

I'm looping in Riley Nguyen to help check the 1PPS configuration. This may take a few days to early next week. She will clarify the timeline.

Regards,

Jennifer

0 Raja Venkateshwaran 3 months ago in reply to Jennifer Bernal

Prodigy 65 points

Hi Riley Nguyen new_config.tcs Here is our latest tics pro file. Awaiting for your reply. We are in time crunch. Hoping you get back us soon.

0 Riley Nguyen 3 months ago in reply to Raja Venkateshwaran

TI__Intellectual 2625 points

Hi Raja,

I will tale a look at the file next week.

-Riley

0 Riley Nguyen 3 months ago in reply to Riley Nguyen

TI__Intellectual 2625 points

Hi Raja,

With 1PPS input, it is recommended to have DPLL LBW < 1/10 of input frequency, so the LBW needed is 0.1 Hz

I see in your config, 100 MHz OUT0 and OUT1 clocks are generated by PLL1_PRI_DIV and PLL1_SEC_DIV. You could use the same PLL1_xxx_DIV for this clock.

Also, this 100 MHz clock can be generated by VCO2 which has higher performance than VCO1. You could use DPLL2 with APLL2 for these clocks.

As XO frequency is high 122.88 MHz, R divider should be enabled to divide APLL3 phase detector frequency down (APLL3 max PDF = 110 MHz). APLL2 and APLL1 max PDF = 125 MHz.

I've updated and checked DPLL lock on my bench. Let me know if the file works on your end.

LMK5B 1-PPS, 122.88 MHz XO, lock.tcs

-Riley

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LMK5B33216: Sync Issue