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LMK04906: LMK04906 STATUS_LD cannot indicate the PLL1&2 look information

Brooke
Prodigy 120 points

Part Number: LMK04906

Tool/software:

Dear team,

Now we use the LMK04906 for our design and we configured our device use the following register value.

R0 (INIT) 0x80160200
R0 0x00140300
R1 0x00140301
R2 0x00140302
R3 0x00143C03
R4 0x00140784
R5 0x80140C85
R6 0x01140006
R7 0x08110007
R8 0x04080008
R9 0x55555549
R10 0x9102412A
R11 0x0401100B
R12 0x1B0C006C
R13 0x3B02848D
R14 0x0240000E
R15 0x8000800F
R16 0xC1550410
R24 0x000000D8
R25 0x02C9C419
R26 0x8FA8001A
R27 0x1900005B
R28 0x0020011C
R29 0x0180031D
R30 0x0200031E
R31 0x001F001F

I think for the PLL1 and PLL2 have been locked after the above configuration. According to my schematic below, the H9 must be on. While now, the H9 is still off.

Could you please help us to double check on your evaluation board?

We use the CLKin2 for the reference with 50MHz sinewave which is coming from the keysight signal generator - N5182B with output power 5dBm.

External VCXO is VX-501-0208-100M0.

  • 0
    TI__Mastermind 32152 points

    Hi Brooke, 
    If possible, please share your configuration file as an attachment so I can dump it on EVM. 
    Attach a .tcs file if possible. 
    "File" -> "Save"

    Is LD_MUX set to PLL1&PLL2 DLD with LD_TYPE set accordingly? 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 120 points

    Hi Vicente,

    Yes, the PLL1&PLL2 DLD with LD_TYPE  have been set accordingly.

    Please fine the register configuration in .txt file and a .tcs file.

    Thanks for your time.

    Fullscreen lmk04906.txt Download 
    R0 (INIT)	0x80160200
R0	0x00140300
R1	0x00140301
R2	0x00140302
R3	0x00143C03
R4	0x00140784
R5	0x80140C85
R6	0x01140006
R7	0x08110007
R8	0x04080008
R9	0x55555549
R10	0x9102412A
R11	0x0401100B
R12	0x1B0C006C
R13	0x3B02848D
R14	0x0240000E
R15	0x8000800F
R16	0xC1550410
R24	0x000000D8
R25	0x02C9C419
R26	0x8FA8001A
R27	0x1900005B
R28	0x0020011C
R29	0x0180031D
R30	0x0200031E
R31	0x001F001F
    lmk04906.tcs

    Best Regards,

    Brooke

  • 0 in reply to Brooke
    TI__Mastermind 32152 points

    Hi Brooke, 
    I checked on EVM - the LD_MUX functions as expected. I am curious now. 
    if you set the LD_MUX to PLL2 DLD  - is the LED now lit? 
    If the device has been programmed correctly - the VCXO connected to OSCIN will always ensure that PLL2 DLD is high and if that's not the case it's possible the part is not being configured correctly. 
    PLL1 is always more difficult to debug as their are many factors that can contribute to it not locking.

    Regards,

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 120 points

    Hi Vicente,

    We have fixed this issue by ourselves.

    We changed the PLL1_WND_SIZE from 40ns to 5.5ns, and the PLL1 has been locked.

    For the PLL1 phase detector freq. is 25MHz in our configuration, and the cycle time is 40ns which is the same time with PLL1 window size. The PLL1 lock counter will increment always. Therefore the PLL1 will never been locked under this condition.

    Thanks for your time. I think we can close this topic.

    Best Regards,

    Brooke