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LMK5C33216: Phase noise spurs in the offset band of 50Hz - 1000Hz when enabling the DPLL3

Christoph Schildknecht
Prodigy 20 points
Part Number: LMK5C33216

Tool/software:

Hi,

We have some troubles with phase noise spurs in the output of the APLL3/DPLL3. When only the APLL3 is active the output phase noise is good, however when we are enabling the DPLL3 then we get some significant phase noise spurs in the 50Hz - 1000Hz offset band. The additional phase noise that occurs when enabling the DPLL is around ~250fs rms due to the spurs.

Our settings is: f_vco = 25MHz, f_ref = 10 MHz, DPLL_BW = 1 Hz, f_TDC = 1 MHz, f_out = VCO3/4 = 614.4MHz (Different DPLL_BW and f_TDC lead to similar results, with slightly different spur frequencies and amplitudes)

We are using TICSPro to calculate the register values.

Is this expected behavior? Or how could we mitigate this issue? For us the 10Hz to 100kHz offset band is of most importance.

Thanks a lot for any help and regards,

Christoph

  • 0
    TI__Expert 3135 points

    Hi Christoph,

    Could you please share the phase noise plot of the output that observing spurs?

    What is the jitter region are you looking at? In the most case, jitter is determined in the range of 12 kHz to 20 MHz so if the spurs are introduced in the region 50 Hz to 1 kHz as you mentioned, it wouldn't impact much on jitter region 12 kHz to 20 MHz.

    In your configuration, f_vco of LMK5C33216 should be 2457.6 MHz. What is the 25 MHz clock for? It helps if you could share the tcs file to review. Thanks.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 20 points

    Hi Riley,

    Thank you for your reply. I have attached the tcs file and a typical phase noise plot, where the phase noise is integrated to the jitter in the 10Hz to 100kHz band. The blue line is the raw signal and the orange one with the spurs removed to see the difference. When the DPLL is deactivated the spectrum has no spurs and in the same band the jitter is around 160fs. The carrier frequency in the phase noise plot is 279.5 MHz. Unlike as in many other cases, the jitter region that we are sensitive to is from 10Hz to 100kHz.

    Ah, and the 25 MHz is the f_xo and not f_vco as stated above, my mistake.

    -Christoph

    ControllerCarrierBoard_external.tcs

  • 0 in reply to Christoph Schildknecht
    TI__Expert 3135 points

    Hi Christoph,

    I'll review the file with my test bench next week.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 20 points

    Hi Riley,

    Thanks a lot. Looking forward to your findings.

    - Christoph

  • 0 in reply to Christoph Schildknecht
    TI__Expert 3135 points

    Hi Christoph,

    In your frequency plan, I do not see 279.5 MHz output. Do you mean 250 MHz?

    The output clock carries phase noise of VCO starting from 10 kHz and above. In the region < 1 kHz, the device references noise of the input (either XO or DPLL input). You could try with smaller DPLL LBW such as 0.1 Hz or 0.01 Hz

    -Riley