• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 21 subscribers
  • Views 125 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK5B33216: Tarana Wireless - Clock Tree Solution

Owen Mears
Expert 4105 points
Part Number: LMK5B33216
Other Parts Discussed in Thread: LMX2487

Tool/software:

Hello,

My customer, Tarana Wireless, provided some information regarding their clock tree for a new program they're developing. Can you take a look and work with me to help provide a few devices or a system-level recommendation for them from TI? Happy to support this ask via a call or however is the team is able to support at this time:

I'm looking to synthesize a 44.8MHz LVDS clock with <60fs jitter from a device that I can lock to a 1PPS or 1MPPS and 25MHz reference with automatic failover to a local XO. I would also like to synthesize 1PPS, 25MHz, 100MHz, 125MHz, 156.25MHz, 166.667MHz and 200MHz but the jitter requirements are only in the 250fs range or greater. I can also synthesize them separately if necessary.

One thing to note is that the jitter specifications are estimates based on the phase noise requirements of our system, however the RMS value is integrated over a non-standard frequency range.

Please see the datasheet of the ASICs that will be driven by this 44.8MHz clock source:

Please let me know if we are able to support this ask! Thanks very much,

Owen

  • 0
    TI__Intellectual 2875 points

    Hi Owen,

    On the input side, LMK5B33216 can lock to the reference 1PPS and 25 MHz. Could you give more details on how the system behavior with "automatic failover to a local XO"? Do you mean a holdover?

    LMK5B33216 can perform holdover during the loss of reference and lock to the XO. Once the reference is back and valid, it re-locks to the reference.

    On the output side, there is a total of 4 clock domains which would require 2 devices since LMK5B33216 can support max 3 clock domains.

    Here is a suggestion for this clock plan using LMK5B33216 and LMX2487. 44.8 MHz is separated to LMX2487 as this clock has tighter jitter spec.

    A typical jitter range that we often see is 12 kHz to 20 MHz. What is the jitter integration range for output clocks? 

    Clocks generated by LMK5B33216 are capable to meet 250 fs.

    What are clock formats neede?

    -Riley