LMK04208: Why 0-day mode can't work?

Hello Jason, 
Are you sync the dividers to ensure all the outputs are synchronized? 
Since you are utilizing zero-delay dual PLL mode? 
The idea becomes you feed CLKOUT0 as reference to the N divider in PLL1 which now ensure CLKINx and CLKOUTx are aligned. 
Given that sync synchronizes your outputs - and one output is in sync with the input now all the outputs are in sync with the input.

You should have deterministic delay every power cycle after performing sync. 

Best regards, 

Vicente

Hi, Vicente:

I only use zero-delay mode (feedback CLKout0 to PLL1) , and don't perform sync. Your meaning is that performing sync is also be needed and together with zero-delay mode to align phase of all CLKouts, right??? 

Application Report named Multi-Clock Synchronization mentioned  two rule of Zero delay mode. 

It also mention that all the other outputs can share the phase determinism by synchronization with the D2 divider in the feedback.

Here, the synchronization is the meaning of performing sync???

My clock plan listed below is conform to the rule totally. Test also find that CLKout0 align CLKin1 determinately, but CLKout1 don't have fixed phase relation with CLKout0

CLKin1: external 7.68MHz sine clock from signal generator

CLKout0: 7.68MHz(internal feedback to PLL1)

CLKout1: 7.68MHz

CLKout2: 122.88MHz

CLKout4: 122.88MH

Thanks in advance!

Best regards!

Jason

Hi, vicente:

Let's continue this thread again, cause I find a new case

During test, when all NO_SYNC_CLKoutX bit =0, I found that all output clocks have been aligned each other after configuring the registers file into LMK04208. But, at this moment I didn't apply external SYNC signal or toggle the SYNC_POL_INV bit yet. I check the methods of Generating SYNC, and programing PLL2_N in the Register R30 will generate a SYNC event automatically as shown in the Figure.1. So, during configuring registers file after power on,  the configuration sequence is from R0 to R31 as shown in the Figure.2.

When R30 was programmed with all NO_SYNC_CLKoutX bit =0, will it generate a SYNC to align the phase of all output clocks ?

Figure.1

Figure.2

Thanks in advance!

Best regards!

Jason