LMK5B12204: Provide the LMK5B12204 configuration scripts

liu billy

Part Number: LMK5B12204
Other Parts Discussed in Thread: LMK5B33216

Tool/software:

Dear

Now I am debug the LMK5B12204 , found that through the TICS PRO software configuration out of the register is a little hard to understand, and the specification book is too far away. The configured tcs file does not run. Do you want to ask your company to help me configure a tcs file? The chip I use is LMK5B12204, and I need several clocks for FPGA, including 222.252155Mhz, 250.303398Mhz, 260.416667Mhz and 277.217742Mhz, which can meet four or two of them. The output is LVDS interface, jitter about 50fs, PRIREF and SECREF frequency and format type and SECREF frequency and format type of FPGA PLL to give out the clock, can be 100M, 125M, meet even times. Could you please help me configure it? or Provide the LMK5B12204 configuration scripts, thanks.

over 1 year ago

0 Kyle Yamabe over 1 year ago

TI__Intellectual 1250 points

Hello Liu,

The LMK5B12204 only has two frequency domains and since the output clock frequencies are all different domains we will only be able to produce two of them using this part.

The device can support the LVDS output type as well as the input reference frequencies and format.

Which 2 output frequencies would you like me to configure?
I can test the two output frequencies and check if it meets the 50fs jitter requirement.

Best Regards,
Kyle Yamabe

0 liu billy over 1 year ago in reply to Kyle Yamabe

Intellectual 630 points

I only need 250.303398Mhz , I need to use the SPI interface and now I just find it a little weird to use the SPI interface with two pins at 1.8V and two at 3.3V

Please give me SPI interface is configured to output 250.303398Mhz and set the output to OUT0 or any one, thanks.

0 Kyle Yamabe over 1 year ago in reply to liu billy

TI__Intellectual 1250 points

Hello Liu,

I will begin working on a configuration for your setup using a 250.303398 MHz output on OUT0. I will test and provide the configuration to you by the end of this week.

0 liu billy over 1 year ago in reply to Kyle Yamabe

Intellectual 630 points

thanks Kyle, By the way,

How many SPI frequency Settings are appropriate?I use the mode 1 according to the specification waveform understanding is correct ?

0 Kyle Yamabe over 1 year ago in reply to liu billy

TI__Intellectual 1250 points

Hello Liu,

I am not sure what is meant by SPI frequency Settings.
If you are asking how many devices are needed to generate the 4 output frequencies you would need 2 LMK5B12204.

I am still working on the configuration but I will send that by the end of this week.

Best Regards,
Kyle Yamabe

0 liu billy over 1 year ago in reply to Kyle Yamabe

Intellectual 630 points

sorry , It is SPI speed, 1M or 40M what is appropriate ? Yes , 2 Devices

0 liu billy over 1 year ago in reply to liu billy

Intellectual 630 points

sorry 1 Devises needed to generate the 4 output frequencies

0 liu billy over 1 year ago in reply to liu billy

Intellectual 630 points

Please check the schematic, FPGA clock

0 Kyle Yamabe over 1 year ago in reply to liu billy

TI__Intellectual 1250 points

Hello Liu,

Attached is the TCS file to configure OUT0 to 250.303398 MHz with a 100MHz XO based off of the schematic and a 100MHz and 125MHz reference.
The jitter performance is also worse then the 50 fs because to configure this output it requires using VCO2 and not just the BAW VCO.
The jitter performance as seen on the phase noise plot image attached is 178 fs.
If the output jitter is a large concern the LMK5B33216 parts have a newer VCO technology that can help reduce the output jitter.

Our SPI clock rate is 20MHz.

Best Regards,
Kyle Yamabe

LMK5B12204 250.3034MHz OUT0 config.tcs

0 liu billy over 1 year ago in reply to Kyle Yamabe

Intellectual 630 points

thanks Kyle

The register list of LMK5B12204 script configuration does not match the data manual. The register list of the script is more than one hundred more than that in the data manual.?Another problem is that the configurator data in the script is configured according to the hexadecimal data, and the FPGA is configured according to the rate of 20M of the SPI interface and the mode one, and it can be successfully sent directly

0 Kyle Yamabe over 1 year ago in reply to liu billy

TI__Intellectual 1250 points

Hello Liu,

Yes the programming manual may not expose all of the registers as there are some registers that are automatically set or are configured automatically when using Ticspro.

I do no understand the issue with the SPI interface and FPGA. Is the data not being transferred correctly?

Best Regards,
Kyle Yamabe

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LMK5B12204: Provide the LMK5B12204 configuration scripts