TPL5010: TPL5010

Hi Michael,

Nice to meet you. Thank you for liking my name.
I have two more questions:
1. According to the following flowchart, if the done signal is stopped after the done signal is given, then the time to the next watchdog reset is Tip + T1?

2. In addition, the customer uses a 20KΩ resistor, and the theoretical time is about 47S, but during the test, it was found that after triggering multiple watchdog resets, there would be occasional reset times lower than 20S. During this period, the TPL5010 chip did not experience power failure. I wonder if you understand this situation.

Thanks

Hi Arabella,

1. That is correct, the time to the next watchdog reset is Tip + T1. The more critical aspect to understand is that if a DONE pulse is not received within Tip of the rising edge of the WAKE signal, the TPL5010 asserts the RSTn signal. 

2. During the shorter reset intervals, does the TPL5010 conclude the interval by pulling RSTn low?

Thanks,

Michael

To supplement the customer's dog feeding logic: the MCU flips the high and low levels of the done pin every 1S. After stopping the dog feeding, the done pin remains at a low level. The dog feeding waveform is as follows:

The following is the waveform of abnormal reset time captured by the customer：

The watchdog resistor is 20k, and the theoretical reset time is about 47S. After the watchdog is stopped, it takes about 138S to trigger the watchdog reset. What is the reason?

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Hi Arabella, 

1. Just to confirm, the issue is that the RSTn asserts low much later than expected? Or does it still assert low earlier than expected?

2. Can you provide an oscilloscope shot with the WAKE signal, as well?

3. Can you send me your schematic? Some timing issues are the result of not having a pull-down resistor wired to the DONE output. 

Thanks,

Michael