Tool/software:
Hi Expert,
I would like to double check can LMK05318B do Jitter attenuation? In a certain application scenario, the customer's input and output clock signals have the same frequency and format, but the jitter margin of the input clock is insufficient. Can we expect the output to have a larger jitter margin?
Regards，
Hailiang
Hi Hailiang,
The LMK05318B can jitter clean if the input clock is noisier than the LMK05318B APLL and VCO noise. In most applications, the input is noisier so the LMK05318B does function as a jitter cleaner.
Please refer to the section: 4.1 Phase Noise Profile in the SNAA396 app note (https://www.ti.com/lit/an/snaa396/snaa396.pdf?). There is explanation of how the reference/input noise impacts the output clocks of a PLL (LMK05318B). The image below shows a generic phase noise plot of a LMK05318B output. You can see that the DPLL reference (REF input) and APLL reference (XO input) dominate the output clock noise below the APLL loop bandwidth (LBW) setting. Beyond the APLL LBW, the APLL and BAW VCO noise dominate the phase noise. The BAW VCO provides exceptional jitter performance for the 12 kHz to 20 MHz integration range.
Regards,
Jennifer
