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LMKDB1104: PCIe clock buffer - PWRGD assertion enquiry

Part Number: LMKDB1104

Tool/software:

I am look for a 1 to 4 PCIE Gen4 clock buffer/fanout,  2 clocks to PCIe add-in card and 2 clocks to AMD FPGA GTY transceiver reference clock

Looking for a simple buffer that do not need much setup, maybe a pin to enable the buffer

Using Clock buffer selection guide, found LMKDB1104/1204, when reading the datasheet, was confused with the description of PWRGD assertion, in the product feature, it says flexible power-up sequence, but based on PWRGD assertion, it will not power-up if clock is invalid, can help to explain what should be the correct start up sequence and the Table 8-1. in 8.3.2.4

8.3.2.3 PWRGD Assertion
The first low-to-high transition of the PWRGD pin after device power is on can occur while input clock is running,
floating, low/low or pulled to VDD. The power-up sequence only starts if the PWRGD pin is pulled from low to
high while input clock is valid.
If the PWRGD pin is pulled from low to high while input clock is invalid, then the power-up sequence is not
initiated and the outputs stay low/low. When this happens, pulling the PWRGD pin back from high to low has no
impact and this low-to-high transition on PWRGD pin is not considered a valid Power Good signal. The device is
powered up next time when the PWRGD pin is pulled high while input clock is valid. In other words, there is only
one valid Power Good signal for every power cycle.

8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
Input clocks can be running, floating, low/low or pulled to VDD when device power is off, regardless of
PWRGD/PWRDN# pin states (low, high, low-to-high transition and high-to-low transition). Table 8-1 shows all the
supported sequences; where clock input can be applied before or after VDD is applied.
Table 8-1. Flexible Power-up Sequences
VDD                         PWRGD/PWRDN#                CLKIN_P/CLKIN_N
Not Present                              X                                   Running
                                                                                       Floating
                                                                                       Low / Low
Present                                0 or 1                                    Running
                                                                                          Floating
                                                                                        Low / Low

Not sure if there are other better option.   Thanks

  • Hello Enging, 
    Yes, your understanding is correct. 
    Upon the first low-to-high transition this pin functions as power good but on subsequent low/high transition the pin functions as power down and the polarity is active low. 

    What the second statement is asserting is the device can take an input when the device is off or VDD = 0V 
    We are only asserting the device will be safe. 
    VDD or CLKINPUT can be applied PWRGD is asserted for the first time, but CLKIN must be available before this assertion. 
    In other words, you can do VDD first followed by CLKIN followed by PWRGD or you can do CLKIN followed by VDD followed by PWRGD

    As long as PWRGD is asserted after CLKIN is available - there is no issue. 

    Best regards, 

    Vicente

  • Hi Vicente,

    Thanks for your feedback.  This would mean I need a control signal to assert PWRGD after CLKIN is available.

    Do you have suggestion of any buffer that would startup with static pin setting?

    Thanks and Regards

    Enging