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LMK03200: Jitter restrain

Ryuuichi machida
Guru 12715 points
Part Number: LMK03200

Tool/software:

Hi,

My customer is suffering from output jitter kinds of cycle t cycle.
In first their sample, they did not observe such jitter.
However, when they created second sample board, they observed kinds of this jitter.

When they create second sample board, they take over same osc and same setting for register of LMK03200.
And, they follow result of "clock design tool" to determine value of "CPout" (loop filter setting.).

Do you have any idea which setting should be checked in this situation ?

BR,

  • 0
    TI__Expert 6135 points

    BR,

    How was the layout modified between the first and second boards? Are the bypass caps as close to the DUT as possible? Did the input reference jitter change? Were the loop filter values changed? 

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    Guru 12715 points

    Hi,

    Thank you for your reply.

    >Were the loop filter values changed? 
    I hear that they did not change loop filter value.

    >Did the input reference jitter change?
    They did not observe any jitter at input side.

    >Are the bypass caps as close to the DUT as possible?
    Which bypass caps do you point out ?
    Do they for power line (Vccxx pins) ?

    >How was the layout modified between the first and second boards?
    In the first board, they created small board which only LMK03200 is implemented.
    And connect this board to main board. The main board have every component for LMK03200 such as cap and res of "CPout", etc.

    The purpose of second board is to implement LMK03200 on main board.
    So, there is no kinds of jumper connection.

    From viewpoint of totally layout, it seems that layout tend to improve.
    But, I do not know detailed difference between first board and second board.

    I am checking datasheet and reference board manual, but it seems that you do not describe kinds of layout guide line.
    Do you have any document which show restriction or recommendation for layout ?

    Best Regards,
     

  • 0 in reply to Ryuuichi machida
    TI__Mastermind 22600 points

    Ryuuichi,

    Can you provide the power portion of the schematic for the LMK03200? It is possible that there is noise on the power that is degrading the performance of the LMK03200. If there is any high frequency signal routed very close to the device, this may also pose an issue.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Guru 12715 points

    Hi,

    I can share not only schematic but also layout.
    However, please share them privately.
    If possible, I would like you to explain each document on web meeting.
    Is it possible to be held web meeting using webex ?

    BR,

  • 0 in reply to Ryuuichi machida
    TI__Mastermind 22600 points

    Ryuuichi,

    Cris and I should be available next Monday (PST) most of the day for a Webex meeting.
    Alternatively, we can move this to internal-only E2E instead of public E2E.

    Thanks,

    Kadeem