Tool/software:
On behalf of a customer:
What are the guidelines for selecting the PFD frequency, loop filter settings, etc... in TICS Pro to achieve lowest possible phase noise?
I read on E2E somewhere that more loop BW is better?
Thanks, -Steve
Thanks; see below- I think this captures what was going on in TICS that needs to be optimized for noise/jitter:
Steve,
I found that reducing the CP gain to 700uA and changing the PLL to Integer mode [see below] improved jitter performance, albeit not by a significant amount compared to your current config.
Some things I want to note about this device:
While the CDCE6214 has low additive jitter, it is not necessarily a jitter cleaner. As explained in this appnote, a narrow PLL bandwidth is needed for jitter cleaning. "Narrow" in this case is sub-10kHz, depending on the performance needed. As an example, the minimum bandwidth of the LMK04832 (a dual-PLL jitter cleaner) is 10Hz. The minimum bandwidth of the LMK03328, a clock generator that can be used as a jitter cleaner, is 200Hz.
The CDCE6214 has a minimum bandwidth of 100kHz. Essentially, while the CDCE6214 can efficiently use an already clean input reference, it cannot clean a noisy input reference very well. This is why the device is described in the datasheet as “medium grade jitter” – it will perform well when the input reference has low jitter, but if there is much noise on the input, it will dominate the VCO on this device.
What is the jitter of the input reference and what is the required output jitter limit? If the input reference is near or below the limit, then we can further work to create a more ideal PLL config.
Best,
Cris
