CDCE6214: LVCMOS TO 144MHZ Script file

In addition, help to reconfigure the single-end 24M into the differential 74.25M

Liu,

To confirm, you need to take a 24MHz LVCMOS input to the CDCE6214 and generate both a 144MHz clock and a 74.25MHz clock? Generating both of these frequencies from a single CDCE6214 is not possible, as 74.25MHz requires a separate frequency domain.

We can provide the configuration for 144MHz differential from 24MHz LVCMOS tomorrow.

Thanks,

Kadeem

Liu,

To confirm, you need to take a 24MHz LVCMOS input to the CDCE6214 and generate both a 144MHz clock and a 74.25MHz clock? Generating both of these frequencies from a single CDCE6214 is not possible, as 74.25MHz requires a separate frequency domain.

We can provide the configuration for 144MHz differential from 24MHz LVCMOS tomorrow.

Thanks,

Kadeem

Hi  Kadeem

    Sorry,  I misstated.

1. We need to input a 24MHZ LVCMOS clock into two different CDCE6214, one output 74.25MHZ clock of LVDS, and another output 144MHZ clock of LVDS.
2. The power supply of both CDCE6214RGER chips is 1.8V, please help to check  the SCH  whether there is any problem . The schematic diagram is as follows

Liu,

I have attached the two configuration files here. Please let me know if a larger swing is required, and we can change the output format from LP-HCSL to LVDS.

CDCE6214_24MHz_In_144MHz_Out.tcs

CDCE6214_24MHz_In_74p25MHz_Out.tcs

For the schematic review, I have two notes:

1. For best performance, I recommend isolating VDD_VCO from the other VDD pins, similar to in the CDCE6214-Q1EVM:
   
2. I notice that you have an additional single-ended 74.25MHz clock on OUT2_P. What is the intention with this? If LVCMOS, this is not available on OUT2, and must be moved to OUT4_P. If single-ended LVDS for testing purposes, OUT2_N must be connected to GND through a 50Ohm resistor. Please let me know so that I may update the configuration.

Thanks,

Kadeem