Part Number: LMX2592
Tool/software:
Hello,
We are using an LMX2592 chip in our project, and we want to be able to set every frequency (with ~1 Hz accuracy) between 100 MHz and 2.5 GHz. We have written our own driver in Python based on a C++ implementation which we found on Github (not tested), information in the datasheet and information from TICS Pro. After power cycling our board, it seems that everything is working accordingly and we can for one time set every frequency which we desire. However, if we don't power cycle the board (e.g. if we reboot it, we restart the application, or we just try to set a new frequency at runtime), we can only get a valid output with a small number of frequencies, and with most frequencies we get no output at all. Every time we start our application, we follow this startup procedure:
1. We soft reset the chip by writing first 0 and then 1 to the 'RESET' field of register 0
2. We write default register values which seem to work for us in descending order:
(First value is the address, second value is the value)
64: 0x0077
62: 0x0000
61: 0x0001
59: 0x0000
48: 0x03FC
47: 0x08CF
46: 0x0FE3
45: 0x0000
44: 0x0000
43: 0x0000
42: 0x0000
41: 0x03E8
40: 0x0000
39: 0x8204
38: 0x0036
37: 0x4000
36: 0x0011
35: 0x021F
34: 0xC3EA
33: 0x2A0A
32: 0x210A
31: 0x0601
30: 0x0034
29: 0x0084
28: 0x2924
25: 0x0000
24: 0x0509
23: 0x8842
22: 0x2300
20: 0x012C
19: 0x0965
14: 0x018C
13: 0x4000
12: 0x7001
11: 0x0018
10: 0x10D8
9: 0x0302
8: 0x1084
7: 0x28B2
4: 0x3F43
2: 0x0500
1: 0x0808
0: 0x221C
3. We read back all registers
4. We write first 0 and then 1 to the 'FCAL_EN' field of register 0
5. We read back all registers again
If we want to change the output frequency, we first determine all the required values, then we write all of the registers (only the ones which have changed) with the new values in descending order and then we run the calibration sequence again. The following values may change when changing the output frequency:
- PLL_R_PRE
- MULT
- PLL_R
- PLL_N_PRE
- PLL_N
- PLL_NUM_LSB
- PLL_NUM_MSB
- PLL_DEN_LSB
- PLL_DEN_MSB
- CHDIV_SEG1_EN
- CHDIV_SEG2_EN
- CHDIV_SEG3_EN
- CHDIV_SEG2
- CHDIV_SEG3
- CHDIV_SEG_SEL
- CHDIV_DIST_PD
- CHDIV_SEG1
- FCAL_LPFD_ADJ
- FCAL_HPFD_ADJ
- PFD_CTL
- CHDIV_DIST_PD
- CHDIV_DISTA_EN
- VCO_DISTA_PD
- CHDIV_DISTA_EN
- VCO_DISTA_PD
- OUTA_PD
- OUTA_POW
- CHDIV_DISTB_EN
- VCO_DISTB_PD
- OUTB_PD
- OUTB_POW
Thank you and we are looking forward to your response.
Kind regards,
Roy



