LMK04828: Require Zero Delay Mode configurations

Hello Pavan, 
This frequency plan is impossible to generate as the Output clocks require an output divider that is an integer divisor . 
A 122.88MHz input for Oscin limits your VCO frequency to 2949.12MHz as the following mathematical relationship must be met: 

Are you willing to use a 100MHz external VCXO for OSCIN? 
If that's the case we can utilize a 2500MHz VCO frequency to generate 100MHz, 12MHz Clock outputs & 3.90625MHz SYSREF out. 

Best Regards, 

Vicente

Hi Vicente,

I am considering only PLL2 now without ZDM.

OSC_in - Connected to 122.88 MHz Crystal with CP0 connection

Output Clocks - 100 MHz, 125 MHz, 

Output Sysref - 3.90625 MHz

Here are my settings from Frequency Planner

I got 3 solutions with low PDF2 values and Score.

Will the PLL2 get locked with these configurations?

Hi Pavan, 
You should be able to get a lock with this but your output phase noise will most definitely suffer due to the PLL2 PFD frequency being small & the N divider being extremely large. 
As mentioned - you're much better off with a 100MHz input. 

Pavan said:

CP0 connection

I am not following what you mean here? Do you mean CPout1? 
Best regards, 

Vicente 

Yes, I mean CPout1.

What will be the value of CPout1 if PLL1 is disabled?

Can I use only PLL2 in my application without any Hardware change ?

Hi Pavan, 
Sorry for the delay - I was 100% sure i responded last week but I guess I shut my laptop before the reply got posted. 

If PLL1 is disabled, you have also disabled the charge pump of PLL1 and thus CPout1 is basically useless. 

If you only use PLL2 you can operate in single loop mode, but you can no longer control the tuning voltage pin of the oscillator with LMK04828. 
So, if the 122.88MHz clock from your input oscillator is stable and clean - you can directly feed this into OSCin. 

Best regards, 

Vicente