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LMK1C1108: Pull-up for clock output and 1G

Hiromu Susami
Prodigy 660 points
Part Number: LMK1C1108
Other Parts Discussed in Thread: TMAG5273

Tool/software:

Hi team,

I am considering using 21 LMK1C1108s to distribute SCLs from one FPGA to 161 TMAG5273s.

Q1. Do I need a pull-up for each output? (It enters TMAG5273)

Should it be connected as shown in the figure below?

https://www.ti.com/lit/an/slva689/slva689.pdf

Q2. Do I need a pull-up for 1G? (Datasheet say" Typically connected to VDD with external pullup resistor", but just to confirm.)

Regards,

Hiromu

  • +1
    TI__Genius 9190 points

    Hi Hiromu,

    Q1: You should pull up your SDA and SCK lines to VCC. The figure provides a good example to follow - pulling up the output of each device will prevent V_OL from swinging too low. 

    Q2: Instantiating an external pull-up will enable the outputs. The internal pulldown and external pull up will serve to bias the pin. Selecting a pull-up that will hold the pin at the high voltage level is ideal.

    Thanks,

    Michael