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Original question:

LMK1C1104: Can a cosine wave signal be as an input signal of LMK1C1104

LMK1C1104: LMK1C1104 minimum vpp when working with sine wave at the input clock

Zeev Leshem
Prodigy 90 points
Part Number: LMK1C1104

Tool/software:

Hi,

I would like to work with LMK1C1104 with sine wave at its input.

The sine wave will go thru 10nF capacitor and 100R pull up/down resistors into VDD=1.8V

The minimum level of the 100MHz sine wave is 0dBm ~ 0.63Vpp

For ease of calculation (and some design margin), lets discuss about minimum level of 0.6Vpp

At LMK1C1104 DS I can see that VIH is 0.7xVDD (1.26V) , VIL is 0.3xVDD (0.54V)

According to application note snaa411 it is written that the set point is Vt, but VIH, VIL are recommended

Does 0.6Vpp that will fluctuate from 1.2V to 0.6V (both not reach VIH, VIL) and swing around Vt=0.9V should work?

PS - I made lab measurements with signal as low as 400mVpp and still get good signal at the output side (with duty cycle of 47%) which is OK.

I'm not sure that I understand the VIH, VIL correctly (DS looks as mandatory, application note looks as a recommendation).

In addition, can you explain regarding the slew rate of the 100MHz as 0.6vpp (+0.3V to -0.3V) - I'm not sure how it should be calculation (and again), is it a solid requirement?

Below is the setup to check the Sine signal (as low as 400mVpp) with 1.8V VDD

Below is the 100MHz 1.8V CMOS output when input sine is 400mVpp

Thanks,

Zeev.

  • 0
    TI__Mastermind 29212 points

    Hello Zeev, 
    Yes, the current DS requirement for Sine wave inputs is for VIH = 0.7 * VDD & VIL = 0.3 * VDD

    If VDD = 1.8V that results in VIH = 1.26V & VIL = 540mV respectively which is exactly what you calculated. 

    This basically means that the minimum required input swing for a Sine wave must be 0.4 * VDD = 0.4 * 1.8 = 720mV in your case. since VDD = 1.8V 

    You need to bias to Vt or VCC/2 to achieve good output duty cycle. 

    The minimum slew rate is as follows:

     

    Assuming your Sine wave has a minimum swing of 600mVpp at 100MHz this corresponds to a slew rate of SR = Vpp * PI* f = 0.6V * PI * 100MHz = 188.459E6V/s = 0.1885V/ns which just barely meets the minimum requirement.

    Your output phase noise will suffer due to this input slew rate. You also get some duty cycle distortion with LMK1C if the swing isn't large enough. 

    I highly encourage you to use a 3.3V Sine wave as this would greatly increase the swing and result in much better output phase noise performance. 
    The input is 3.3 tolerant regardless of whatever VDD is. 
    Currently you're not meeting the minimum swing regardless. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 90 points

    Hi Vicente,

    Unfortunately, I can't go to 3.3V.

    My TCXO worst case power is 0dbm (~0.63V for 50 ohm).

    If I change the pull up/down to 200 ohm each (100 ohm effective at the end of line) I will get 0.89Vpp.

    This should be higher than 0.72Vpp (0.4xVDD) which should also have higher slew rate

    Do you think this is acceptable solution, any issue with this?

    Why does 0.188V/ns barely meets the spec (it is almost 88% above the minimum)?

    Thanks,

    Zeev.

  • 0 in reply to Zeev Leshem
    TI__Mastermind 29212 points

    Hi Zeev,
    As long as you meet minimum swing of 720mVpp or 0.4xVDD you should be good. 
    Sorry my mistake you're correct you meet slew rate - just know our jitter values assume 2V/ns input slew rate for best output phase noise. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 90 points

    Hi Vicente,

    Something is not clear regarding the 2V/ns:

    Since 0.6Vpp is 0.188V/ns than 6Vpp is 1.88V/ns (closer to 2V/ns which assume the best output phase noise according the information from your reply).

    But 6Vpp is +3V to -3V that sits on DC level (set by the VDD/2 resistors). I don't see any Vt threshold level that is relevant for that. 

    Moreover, this will violate the absolute maximum rating of +3.6V to -0.5V.

    Assuming VDD=3.3V than VDD/2 is 1.65V which allows no more than 1.95V (not to reach 3.6V), than the maximum Vpp is 1.95V*2 = 3.9V

    3.9V at 100Mhz is roughly 1.2V/ns, but the application notes show some results for 100MHz at some use cases (it can't be with 2V)

    The LMK slew rate at data sheet is defined from 20% to 80% - maybe sine formulas are different?

    What am I missing here / not understanding?

    Thanks,

    Zeev.

  • 0 in reply to Zeev Leshem
    TI__Mastermind 29212 points

    Hi Zeev yes for Sine wave formula is different it’s the one I attached previously.

    The 2V/ns spec in DS is using a square wave input.

    best regards,

    Vicente