LMK04808: LMK04808 - Speed and Configuration Time of Micro-wire Interface

Hello Sam, 

Here is the response I got from our design team. 
"For the microwire transfer rate, most accesses will be tECS+32x(tCWH+tCWL)+tCES+tEWH. This ends up being 25ns+32x(25ns+25ns)+25ns+25ns or 1675ns per register transfer (though some registers require 3 extra clocks after LE goes high for certain values, but I would treat that as a second write unless I was really pressed for time)

But at the end of the day, the entire configuration will likely be very much faster than the lock time of the PLL unless they have a fast loop bandwidth and a lower than 60-degree phase margin.'

Note section 6.6 of DS has the timing diagrams. 
Given this device does not have a crystal driver the reference is assumed to come up with or before the part and therefore is not part of the time from "start to clock out". 
This device needs to be user configured and the amount of register writes you need to need to do also matters for your use case. 

To summarize - it will come down to have many registers you need to write and which the loop bandwidth is. 

Best regards, 

Vicente