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LMX2820: SPI block transfer

Christer Andersson
Intellectual 290 points
Part Number: LMX2820

Tool/software:

Hi,

Does the LMX2820 support some sort of SPI block writing of contiguous registers? I'm looking at calculating how long time it will take to do the SPI transacations to change frequency with instant calibration.

My current take is that if I enable register double buffering I should be able to write the following registers to change frequency:

  • PLL_NUM (0x2A, 0x2B) + INSTCAL_PLL_NUM (0x2C, 0x2D) -> 8 addr + 4*16bit data = 72 bits
  • PLL_DEN (0x26, 0x27) -> 8 addr + 2*16 data = 40 bits
  • PLL_N (0x24) -> 8 addr + 16 data = 24 bits
  • R0 (0x0) -> 8 addr + 16 data = 24 bits

In another forum post I saw a TI representative mention they are quite confortable that SPI can run at 60 MHz (and that they might update the datasheet).

This gives me an indication that writing the 160 total bits will take roughly 160/60 = 2.7 us (ignoring the minimum 13 ns chip-select toggling margins between SPI transactions).

So my basic questions are:

  • Does LMX2820 support block SPI? E.g. just keep transferring additional 16-bit data words after the initial starting address?
  • Is the 60 MHz SPI speed assumption valid?

Thanks,

Christer

  • +1
    TI__Guru** 108270 points

    Hi Christer,

    Block programming is supported but the registers must be in sequence. For example, R31, R30, R29, ..... 

    Block programming does not work with random sequence, e.g. R31, R14, R1, R0. 

    60MHz is valid. 

  • 0
    TI__Mastermind 33730 points

    Supplemental to Noel's answer:

    Block programming is supported, in either ascending or descending address order. The default is descending; you can set R0[11] = 1 to change it to ascending. Taking the PLL_NUM + INSTCAL_PLL_NUM block as an example: in descending order, you write 0x2D -> 0x2C -> 0x2B -> 0x2A; in ascending order, you write 0x2A -> 0x2B -> 0x2C -> 0x2D.

    CS# stays low until the end of each block. So the 0x2A to 0x2D block, CS# stays low for all 72 bits; for the 0x26 to 0x27 block, CS# stays low for 40 bits; etc. CS# rising edge clears the block programming address pointer - in other words, you always have to specify a starting address at the beginning of every SPI transaction. This likely matches what you already assumed (how else would it work?), but I write it out for the sake of explicitly documenting it.

  • 0 in reply to Noel Fung
    Intellectual 290 points

    Thanks guys, then it works as I would hope.