Hello, I am using the SPI port to control a cdce72010. My goal is to take in the AUX CLK input and use it to drive the dividers directly, leaving the pll off and the FB divider off. My registers are programmed to the values below (read back from the device), but I do not get a clock out of the part at all in this mode. I have successfully configured it for an 800mhz vcxo and a 100mhz primary reference and secondary reference, but the ext clk just doesn't seem to work. Any insight is greatly appreciated.
READ: Addr = 0, reg val = 0x683C0310
READ: Addr = 1, reg val = 0x68000020
READ: Addr = 2, reg val = 0x83060002
READ: Addr = 3, reg val = 0x68000002
READ: Addr = 4, reg val = 0xE9800004
READ: Addr = 5, reg val = 0x68000004
READ: Addr = 6, reg val = 0x68000006
READ: Addr = 7, reg val = 0x83400016
READ: Addr = 8, reg val = 0x68000098
READ: Addr = 9, reg val = 0x68050CC8
READ: Addr = 10, reg val = 0x09C0270A
READ: Addr = 11, reg val = 0x8280044A
READ: Addr = 12, reg val = 0x60009B0C
