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LMK03806: Jitter Performance

Ryan Larson
Prodigy 70 points
Part Number: LMK03806
Other Parts Discussed in Thread: LMK03328

Tool/software:

Hello,

I am planning on using the LMK03328 in our design. I have some questions relating to the jitter performance. Is jitter performance different if I use a 100 MHz reference clock vs a 50MHz crystal? 

Also, do I have to use the SECREF input? Can I still use PLL2 with the SECREF input disabled? If so, what is the purpose of having this input? 

Lastly, TICSPro says I can make this configuration work with a single PLL. I don't see how that is possible. See the image for my configuration.

Thanks,

Ryan

  • 0
    TI__Mastermind 22360 points

    Ryan,

    1. Performance will (generally) be better with a higher PFD frequency, though if there is substantial noise on the input this will not be fully filtered out at the output clocks.
    2. SECREF does not have to be used. Either SECREF or PRIREF can be used as the input to both PLLs. There are some cases where a primary clock is used, with SECREF as a backup clock in case the first clock is lost (switchover). There is also the use case where the device is used as a jitter cleaner - a noisy clock is provided through one input, a narrow loop bandwidth PLL is used to clean the clock to one of the outputs, and then this clock is used as the input for the second PLL.
    3. Your configuration should allow for using a single PLL operating at 5000MHz, with a post-divider of 2 for 2500MHz at the input to the output dividers. This can be divided by 16 for 156.25MHz, by 20 for 125MHz, and by 25 for 100MHz. Set each output to be sourced by PLL1, then set the dividers to the values listed here. On the Inputs/PLL page, PLL2 can be disabled.

    Thanks,

    Kadeem