LMK04610: Clock & timing forum

Output to output skew on the same device has a max of 95ps. The variation in part-to-part skew, even for the same output, is 100s of ps across PVT. The propagation delay variation over temperature for a single output is also 100s of ps, but the output blocks are at roughly the same temperature during operation and have roughly the same propagation delay temperature coefficient, so they tend to skew together - nevertheless, the skew between outputs should not be treated as constant across temperature.

The part is still active, we still support it, it just did a lot differently from most of our other PLLs and that makes it challenging to work with and to support. It was designed with a very specific use case in mind, and other use cases tend to encounter one or more unusual difficulties. The reason it can be so low power is because of a novel semi-digital PLL architecture, but that same architecture results in PLL1 wander even while locked, which is well-documented across the forum; other implementation choices like the use of a primarily-CMOS process instead of a BiCMOS process led to large propagation delay variation across temperature relative to our BiCMOS PLLs like LMK04828 or LMK04832, which can be surprising for people trying to use it in applications where skew and prop delay variation should be minimal; and there are several unexpected limitations, like the relationship between SYNC/SYSREF triggering and PLL2 PFD frequency, which are occasionally a nuisance - in this case, it would seem, a highly relevant nuisance.

The SYNC and SYSREF triggers are re-timed by the output of the VCO post-divider. If you do not have the post-divider engaged (i.e. the VCO on), the SYNC and SYSREF cannot be activated. Additionally, there is a re-timer on the GLOBAL_SYNC and GLOBAL_SYSREF signals as well as the signals generated by the SYNC pin, which implies that PLL2 must be on (even if not locked) and a reference signal must be applied to PLL2, in order to use the SYNC or SYSREF behaviors. This device is not designed to function as a pure clock + SYSREF distribution passthrough buffer. If you really want to make LMK04610 work this way, using only the documented register set, you need to enable PLL2, lock it to synchronize the VCO post-divider with the clock distribution signal, and also route PLL2 CLKin to the output channels. If the SYSREF frequency exceeds the state machine clock divider frequency, the SYSREF will not trigger reliably; meanwhile, the state machine frequency is strictly a power-of-2 divider from the PLL2 reference clock (see PLL2_REF_DIGCLK_DIV field) with a maximum divide of 32 and a maximum frequency of 50MHz, meaning there are cases between 50MHz and 25MHz where the SYSREF cannot be reliably generated at all. Incidentally, the SYNC is also re-timed by the PLL2 reference clock-derived state machine clock and the VCO post-divider, so aligning the dividers initially also requires PLL2 to be enabled.

I think there are some override bits in register 0x148 that can force an asynchronous SYNC and SYSREF trigger signal without all the retiming through PLL2 and the VCO post-divider - setting 0x147 to 0x0C and 0x148 to 0x03 should force a trigger to the SYNC and SYSREF of each enabled channel, respectively, but I haven't tested this, and it's not necessarily guaranteed to work since it isn't production tested (though if the method is correct, it's extremely unlikely to fail in practice, since it would take an incredibly specific defect). Assuming this works, you could at least generate asynchronous SPI triggers for both SYNC and SYSREF - it would be sufficient for a single-device use case where there's no timing-critical window for the SYNC or SYSREF to be generated. If this isn't good enough, i.e. if you have to deliver the SYNC or SYSREF signals at a specific moment, or if you have multiple LMK04610 devices to synchronize, you would have to temporarily enable and lock PLL2 at startup or whenever a SYSREF pulse must be generated.

For power consumption, consult table 226 in the datasheet. Any block you don't have enabled can be treated as nearly-zero current consumption (<1mA).