LMX1214: Jitter & rise/fall time

For 1 and 2, use PLLatinum Sim to model the jitter effects of LMX1214 on arbitrary inputs. In "intermediate" feature level or greater, the CLKIN noise source can be loaded as an external comma-separated text file: column 1 as carrier offsets in Hz, column 2 as phase noise in dBc/Hz. Our input test sources had less than 1fs jitter at 6GHz carrier, measured from 1kHz to 20MHz; our output measured around 1.5fs with the same input source at the same frequency.

For 3, LMX1214 is a buffer with an optional divider. The input frequency range is from 300MHz to 18GHz, and it will output a signal with identical frequency tolerance.

For 4, I recommend the highest possible slew rate, preferably >5V/ns at each input pin. Jitter performance is highly dependent on fast input slew rate.

You need to set the upper limit of integration to less than the carrier frequency. In your screenshot it was set to 2.5GHz, but the carrier is only 450MHz.

I don't predict the LMX1214 CLKOUT outputs will add any noticeable phase noise degradation to the output of an LMX2582. But the LOGICLK output might add some noise due to the elevated noise floor when using LVDS or other non-CML formats (because the LOGICLK output buffer is optimized for driving FPGAs or other less-critical phase noise targets).

The output divider in LMX2582 does add to the noise floor relative to the pure VCO output. If the desired output frequency is high enough that it can be generated using the divider in the LMX1214, I recommend driving LMX1214 from LMX2582 at a frequency that exclusively uses the integrated VCO and not the channel divider for better noise floor performance. If the desired CLKOUT frequency is 450MHz (and not just the LOGICLK), A direct VCO configuration can just barely be achieved on LMX2582 with 3600MHz VCO and LMX1214 divide-by-8.