LMX2582: Support on PLL rise time/Fall time, Phase Jitter, frequency tolerance, Input Duty cycle/High time

Hello,

The team is out for the holidays. Please expect a response by Jan 2 at the earliest.

Thanks,

Kadeem

Gentle reminder looking forward to your reply.

1.  What is the rise time/fall time on input pins (OSCIN P/M) ?

 ->  This is a characteristic of the input signal, not the device.  Our device prefers a higher slew rate for the best phase noise though.  For the absolute best phase noise, you want 500 V/us, but we can function at much lower, like 100 V/us or even much lower than this.

2. What is the rise time/fall time on Output pins (RFOUTA/B_ P/N) ?

 I don't have a measurement for this, but it's quite fast as these outputs work in the high GHz range, so under 50 ps, likely much lower.

3. What is the Input Duty cycle or High time  on input pins (OSCIN P/M) ?

 -> If the input doubler is NOT used, we can tolerate a pretty low duty cycle, 30% no problem.  It's triggered on the rising edges of the signal.  However, if you are using the inptu doubler, then if you have poor duty cycle, this will create spurs at the output as this tracks both rising and falling edtes.

4.What is the Phase Jitter (Min/Max) values on Input pins (OSCIN P/M)?

 ->  You can put 1000's of fs of jitter easily on the input, but this jitter is attenuated and transferred to the output. PLLatinum Sim can simulate this at ti.com/tool/PLLATINUMSIM-SW

5. What is the Phase Jitter (Min/Max) values at Output Pins (RFOUTA/B_ P/N)?

 -> we give no min/max limits as this is very configuration dependent.  With a 100 MHz input, we can get on the order of 70 fs of jitter for a clean input reference and optimized loop filter.

6. What is the Output Frequency tolerance at Output Pins (RFOUTA/B_ P/N)?

-> It tracks the input reference perfectly.  So if your input is exact, so is the output, if the input is 1 ppm too high, so is the output.

Regards,

Dean