LMK1C1104: Generating non-50% duty cycles

Hi Prasoon,
That's correct - Unfortunately we don't have clock buffers capable of generating 4 different duty cycles at the same time. 

Best regards, 

Vicente 

Hi Vicente,

Thanks. I understand.

Any recommendations on extending this to the 600MHz-1GHz range in frequency? 

Hi Prasoon,

At that frequency range you would need to use differential signaling as most LVCMOS outputs orly go up to 250MHz 

Best regards,

vicente

So far I think we've failed to answer the central question - is there a way to generate the various duty cycles of signal required?

As far as I can tell, there is no purpose-built custom duty cycle CMOS pulse IC of this nature. You'd need to build something yourself. 

Part of the challenge here is, generating a 10% duty cycle pulse for a CMOS output is effectively a requirement to produce a signal 5x higher bandwidth than desired. Your 250MHz ceiling is substantially more intimidating at 10% duty cycle, where the effective bandwidth is 1250MHz. Considering also that CMOS signals are supposed to be square-ish waves, and square waves are the Fourier sum of higher-order harmonics, let's say we need at least up to the 5th harmonic to be mostly-unattenuated to get something resembling square-ish, which is 6750MHz. The actual output bandwidth required for your 10% duty cycle 250MHz output is around 1.4 orders of magnitude higher than the periodic interval of your pulse would suggest. This is very challenging to achieve with CMOS. There's no 74-series logic that will help with this requirement, because the propagation delay and slew rate of these devices are not designed for extreme duty cycles or transmission line drivers. Some vendors do sell GHz-rated logic components, and they mostly operate with differential inputs and outputs (not TI - a few offerings exist among Microchip, OnSemi, or former Hittite (now Analog Devices)). You could also utilize slightly more complex devices like D-flip-flops and T-flip-flops from the same vendors to achieve similar effects to a logic gate - I leave the specifics of how to do this with more complex logic devices to you.

There's no straightforward solution for your problem, but one approach might be to use a digital delay buffer like LMK01000 or LMK04832 in distribution mode, along with the ability to synchronize the output dividers to independent edges of the clock distribution path, to align two outputs in such a way that you can apply a logic gate to the high-speed differential clock outputs at nominal 50% duty cycle to achieve a comparable duty cycle. For example, to generate a 100MHz output with 10% duty cycle, you could use a 1GHz distribution mode clock, divide the output to 100MHz twice, and phase shift one of the outputs by four 1GHz clock cycles - then apply an AND to the output.

As for how to turn the output into CMOS again, you could attach a high-bandwidth differential to CMOS buffer like SN65LVELT23 or OnSemi MC100EPT21, or you could design your own amplifier stage that can emulate CMOS output levels from the differential input signal.

At higher frequencies, it is still possible in principle to utilize the same scheme described above, but the bandwidth requirements will make most logic components prohibitively slow, and you're certainly going to need a high-speed differential signaling standard like LVPECL or CML as you've already observed. Our delay buffers no longer can natively operate with 10GHz clock distribution paths, so you may need to resort to two independent synthesizers like LMX2594 or LMX2820, and use the fractional divider MASH seed to adjust the phase of the output between two synchronized devices. Alternately, you could use high-speed DACs like DDS39RF10 and some pulse shaping/filtering to synthesize an approximately-square output. In either case, you are left with the challenge of how to perform a high-speed logic gate operation on the outputs to generate the desired output duty cycle, and how to convert this shape into a nominally square pulse for use on a transmission line. I suspect at 1GHz there's no IC which will do differential to single-ended conversion. A balun on a differential output might work if the balun is wide-bandwidth and the pulses are continuous, though single-instance pulses probably wouldn't be an option. Otherwise you're left with the task of making your own amplifier stage.