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LMX1204: Min input frequency

Barak Dror
Prodigy 170 points
Part Number: LMX1204
Other Parts Discussed in Thread: LMKDB1104, LMK04832, LMK1D1204, LMK1D2104

Tool/software:

Hi

According datasheet, the min frequency for CLKin is 300MHz:

1)  Can you explain why can't the device work at lower input frequency?

2)  I'm working in bypass or divider mode, is there any ability to work in lower CLKin frequencies?

BR,

Barak

  • 0
    TI__Genius 17620 points

    Hello,

    The team is out for the holidays. Please expect a response by Jan 2 at the earliest.

    Thanks,

    Kadeem

  • 0
    TI__Expert 3090 points

    Hi Barak, 

    1) The LMX1204 is a radio frequency buffer - meaning that it is designed for frequencies in the GHz range. 

    2) It is not possible to output a frequency less than 150 MHz to a CLK output. 

    It seems that this device may be a bit too robust for what you need, I would recommend a non-RF buffer, such as the LMKDB1104.

    Thanks,

    Michael

  • 0
    TI__Mastermind 31510 points

    Let me expand on that a bit:

    1) Since the LMX1204 was designed to operate at high frequency, the input stage amplifier chose an architecture that uses an internally AC-coupled scheme. The impedance of the AC-coupling network inside the amplifier is such that there is very little headroom internally between positive and negative inputs at the input amplifier. This is mostly fine since there is limited hysteresis to help keep the state of the input stable (though I make no guarantees at DC since mV-scale input noise could change the input state), but it will negatively impact the phase noise since the amplifier benefits from having a large initial input variation from one clear input state to the other.

    Additionally, the SYSREF and windowing circuits were designed around the 300MHz minimum. Realistically, the windowing circuit is probably unnecessary at low frequency, so not having access to the windowing circuit might not be a problem; but the delay circuit for the SYSREF outputs does depend on this minimum frequency being satisfied. At lower frequencies, the delay codes will see greatly increased INL, and some codes may no longer change the delay.

    2) Not without sacrificing phase noise performance, and potentially opening up the possibility of noise-related input glitches; and even then, some features are degraded or unusable (as detailed above in the SYSREF portion).

    We have devices like the LMK04832 which can accomplish a lot of the same effects at lower frequencies, though the skew, propagation delay variation, and delay adjustment capabilities are inferior to the LMX1204. We also have buffers like the LMK1D2104 or the LMK1D1204 which have very good output-to-output skew and can fan out device clocks and SYSREFs at lower frequency from a single source, though the part-to-part skew as a function of process is generally larger and the delay variation options are limited.

  • 0 in reply to Derek Payne
    Prodigy 170 points

    Thanks for the answer.

    I design a board that can be used in various systems. I use the LMX1204 to drive clocks & sysrefs to high speed ADCs/DACs.

    In most cases since phase noise is critical, I use external GHz clocks from a very clean source. For minority of the cases, phase noise is less important, and at system level it's easier to provide low frequency reference and use internal PLL inside ADC/DAC to multiply it. Since it's the same board, I need to take into consideration that slowest reference clk is limited to 300MHz. 

  • 0 in reply to Derek Payne
    Prodigy 170 points

    Hi Derek

    You mentioned that SYSREF and windowing circuits were designed around the 300MHz. As I understand, since max step size is 28pSec, and capture window is 32bit, min clk is 32b*28p=~1.1GHz.

    How can a 300MHz can be measured?

    BR,

    Barak

  • +1 in reply to Barak Dror
    TI__Mastermind 31510 points

    The windowing circuit has no frequency limit per se (it is still possible to measure a CLKIN edge timing at 300MHz, but there are necessarily phase limitations for that measurement). But the CLKIN AC-coupling can cause the windowing circuit to behave quite strangely at lower frequency. It's also worth pointing out that 28ps maximum step size of the windowing circuit is a typical value, and the step size could vary by around 15% across process - in practice this means that the upper frequency limit to reliably capture a full period of CLKIN within the windowing circuit is more like 1.4GHz.

    300MHz is the floor on the SYSREF delay divider input. The SYSREF delay generators use what amounts to a ramp generator (current source + capacitor), a DAC, and a comparator internally to generate the retiming edge for the SYSREF outputs. The size of the capacitor in the ramp generator is inversely proportional to the output frequency of the SYSREF delay divider. A mode exists in the device to utilize a delay divider output between 150MHz and 300MHz; anything below 300MHz CLKIN falls outside of the usable range of the delay generator, and delay steps become non-monotonic.