Tool/software:
We’re tracking down an FPGA problem and had a question about the Clock Synth. When the documentation says that it does a “hitless switchover”, that means that when the Primary (or secondary) reference is detected, the output will begin using that reference and the output clock will be seamlessly switched, right? Like completely invisible to an outside observer, except the PPM and drift will begin to match the new reference, right?
Is the only way to detect this is if one of the LOR signals trigger correct?
