state of output clocks of CDCE62005 when power down_n pin is asserter (pulled LOW)

Hi Anil,

Yes, the outputs are tri-stated when Power_DOWN_n pin is low. However, the EEPROM cannot be programmed in this state because the SPI is also disabled.

Best regards,

Matt

Hi Matt ,

Thanks for the info. The datsheet of CDCE62005 (table 15 , page 37) mentions that the SPI port is ON in Power_Down State, but your comment mentions that the SPI port is OFF. Can you please reconfirm this. This feature is very important for our system as we are planning to programm the CDCE chip via a host processor when it is in Power_Down State (i.e. Power_Down is pulled LOW) The processor programms the EEPROM via SPI port and than pulls the Power_Down signal to HIGH.

Awaiting your comments.

Thanks ,

Anil

Hi Matt ,

I just realised that i was referring to an older version fo the datasheet which wrongly mentions that the SPI port will be ON during Power_Down state. The latest version has corrected this and mentions that the SPI port is indeed disable during Power_Down .

Do u suggest any other approach where we can programm the clocks outputs in power down state. Our main concern is that the default clocks generated when the CDCE is brought out of Power_Down may damage the processor that take these clocks as inputs. We want to ensure that the clocks are valid and in the specified range for the processor before we bring  the CDCE chip out of Power_Down

-Anil

Hi Anil,

Here is one approach: Power up the device holding the SYNCn pin low. This holds the outputs of the device in HiZ. Write to all of the SPI registers. Once the SPI registers have all been written and the input clock is stable, calibration can be initiated by writing Register 6 bits 27 and 22 (see datasheet page 67 for details). After calibration, the SYNCn pin can be released or set high to enable the outputs.

Best regards,

Matt