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Tool/software:
Hello,
My customer wants to use CDCM7005 under the following conditions. Is it possible?
- VCXO_IN = 122.88MHz / PRI_REF = 1 PPS(GPS/IEEE1588) / Output Clock = 30.72MHz
Thank you.
JH
Hi JH,
Yes,
We can utilize a R divider of 25 & and N divider value of 3072 to achieve a 0.04MHz PFD which should achieve lock.
Please note detection circuitry is unavailable at a frequency this low according to note in DS.
Please note a newer better performing jitter cleaner such as LMK04828 or LMK04832 can perform this function as well.
CDCM7005 is a cheaper alternative as the cost of phase noise. CDCM7005 is also not supported in PLLatinumSim where as LMK0482x family is.
Best Regards,
Vicente