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LMK04832: Multiple LM04832 SYNC

new2day
Expert 1950 points
Part Number: LMK04832


Tool/software:

Hi

I have two LMK04832 in the system. I have also read the document of Synchronizing multiple LMK0482x devices, or providing more JESD204B outputs than a single LMK0482x device allows.

#1 PLL Outputs

1. The Device Clock (CLKout0 to CLKout8) at 100MHz while Device Clock CLKout10/CLKout12 at 156.25MHz. 

2. All SYSREF outputs (CLKout1 to CLKout13) at 1.25MHz. Which divisible by both 100MHz and 156.25MHz. 

#2

Outputs alignment from two LMK04832

1. If PLL is set to single loop 0-delay mode with FBMUX to CLKout8, the Device Clock outputs are aligned without toggling the SYNC.

2. However the SYSREF are not. 

3. I know that the FBMUX should be set to SYSREF, however the PLL2 won't be locked if do so. 

#3 

REF CLK IN for single loop 0-delay 

1. Does OSCin have to be used for this mode? 

2. Could CLKin1 be used? It seems OK from TICS Pro, the PLL1 and 2 window (or Pan)

3. If FBMUX set to SYSREF, what are the settings for PLL2 (PLL1), such as PLL1 NCLK MUX, PLL2 RCLK MUX, PLL2 NCLK MUX etc.

4. The TXT file is attached, see below. It'll be great appreciation if TI experts can suggest what to be changed.  

#4

About SYNC pin or SPI SYNC.

1. Does SYNC pin must be used in our case? 

Fullscreen default_to_single_clkin1_pll2_100m_vco0_2500m_pll1LD_to_pll2LD_CLKin0_to_CLKin1_sysrefMUX_clk8clk10out156m25_anp511_0730_0814try_2c_0827b_0904.txt Download 
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x01010A
R258	0x010200
R259	0x010340
R260	0x010410
R261	0x010500
R262	0x010601
R263	0x010715
R264	0x010819
R265	0x01090A
R266	0x010A00
R267	0x010B40
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011019
R273	0x01110A
R274	0x011200
R275	0x011340
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x0117C5
R280	0x011819
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011FF5
R288	0x012019
R289	0x01210A
R290	0x012200
R291	0x012340
R292	0x012400
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012810
R297	0x01290A
R298	0x012A00
R299	0x012B40
R300	0x012C20
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013010
R305	0x01310A
R306	0x013200
R307	0x013340
R308	0x013420
R309	0x013500
R310	0x013601
R311	0x013711
R312	0x013801
R313	0x013903
R314	0x013A07
R315	0x013BD0
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013FA3
R320	0x014081
R321	0x014100
R322	0x014200
R323	0x014319
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F13
R352	0x016000
R353	0x016101
R354	0x0162AC
R355	0x016300
R356	0x016400
R357	0x016505
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x016801
R1365	0x055500

Hope to hear from ASAP. Thank you very much.

  • 0
    TI__Genius 9460 points

    Hello,

    To phase align the SYSREF and CLK outputs, you need to toggle the SYNC. 

    Furthermore, setting the FBMUX to SYSREF does not guarantee that PLL2 will not lock - especially if your SYSREF value is less than your PFD2 value, and cannot be divided to produce that value, as a result (in my attached config, I have used DCKLOUT8 as the feedback signal, instead). 

    OSC_IN does not have to be used as the input for the single loop 0-delay mode. You may also use CLKinX as the reference for PLL2.

    If FB_MUX is set to SYSREF, then the PLL2 NCLK MUX has to be set to FB MUX. PLL2 RCLK MUX needs to be set to the signal you plan on inputting to the second PLL, but otherwise, that is all of the settings. 

    Finally, you do not *need* to use the SYNC pin. You may also trigger SYNC functionality internally. You *will* need to trigger a SYNC event to achieve phase alignment among all of the outputs. 

    Regarding the hex file, I have altered it so that you can have the desired output frequencies. I have attached it both as a hex file and as a .tcs file.

    updated_singleloop_0delay.tcs   

    Fullscreen HexRegisterValues_4832.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x01010A
R258	0x010200
R259	0x010344
R260	0x010430
R261	0x010500
R262	0x010601
R263	0x010715
R264	0x010819
R265	0x01090A
R266	0x010A00
R267	0x010B44
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011019
R273	0x01110A
R274	0x011200
R275	0x011344
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x0117C5
R280	0x011820
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011FF5
R288	0x012019
R289	0x01210A
R290	0x012200
R291	0x012344
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012810
R297	0x01290A
R298	0x012A00
R299	0x012B40
R300	0x012C20
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013010
R305	0x01310A
R306	0x013200
R307	0x013340
R308	0x013420
R309	0x013500
R310	0x013601
R311	0x013711
R312	0x013801
R313	0x013903
R314	0x013A07
R315	0x013BD0
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013FA3
R320	0x014081
R321	0x014100
R322	0x014200
R323	0x014319
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F13
R352	0x016000
R353	0x016101
R354	0x0162AC
R355	0x016300
R356	0x016400
R357	0x016505
R358	0x016600
R359	0x016700
R361	0x016958
R362	0x016A20
R363	0x016B00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R388	0x018480
R389	0x018500
R392	0x018800
R360	0x016801
R1365	0x055500

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Expert 1950 points

    Hi Michael,

    Appreciate the quick response. 

    1. I like to confirm again, no need use SYNC pin for multiple device (multiple LMK04832) SYNC in single loop 0-delay mode to have all outputs aligned, right?. 

    2. Should PLL2R_SYNC_EN be set ('1')?  

    3. In your tcs and txt file, CLKin0 is 40MHz and OSCin is 92.5MHz. Can they be 100MHz?

    4. They look different when I re-export again from your tcs file. 

    Thank you very much.

    Fullscreen HexRegisterValues_4832_reExported.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x01010A
R258	0x010200
R259	0x010344
R260	0x010430
R261	0x010500
R262	0x010601
R263	0x010715
R264	0x010819
R265	0x01090A
R266	0x010A00
R267	0x010B44
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011019
R273	0x01110A
R274	0x011200
R275	0x011344
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x0117C5
R280	0x011820
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011FF5
R288	0x012019
R289	0x01210A
R290	0x012200
R291	0x012344
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012810
R297	0x01290A
R298	0x012A00
R299	0x012B40
R300	0x012C20
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013010
R305	0x01310A
R306	0x013200
R307	0x013340
R308	0x013420
R309	0x013500
R310	0x013601
R311	0x013711
R312	0x013801
R313	0x013903
R314	0x013A07
R315	0x013BD0
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013FA3
R320	0x014081
R321	0x014100
R322	0x014200
R323	0x014319
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F13
R352	0x016000
R353	0x016101
R354	0x0162AC
R355	0x016300
R356	0x016400
R357	0x016505
R361	0x016958
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R358	0x016600
R359	0x016700
R360	0x016801
R1365	0x055500

  • 0 in reply to Michael Srinivasan
    Expert 1950 points

    Sadly, SYSREF outputs are not aligned by using your txt file attached. 

  • 0 in reply to new2day
    TI__Genius 9460 points

    Hello,

    To respond to your previous post, you do not need to use the SYNC pin to synchronize the outputs, but you must generate a SYNC event if you want your outputs to be phase aligned. Please see section 8.6.2.3.10 of the datasheet regarding how to set up a SYNC event. 

    You can set PLL2R_SYNC_EN to 1, but you should not need to. Your values are sufficient. 

    You can set CLKin0 and OSC_IN to be whatever you like, but you may only use one signal as the input to the R divider of the second PLL. 

    Using the .tcs file can actually import and export the input values, whereas exporting through the use of the hex file cannot do that. 

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Expert 1950 points

    Hi Michael,

    I found the SYSREF "SYNC" process on E2E.

    I have one thing like to confirm with you, it's PLL2_NCLK_MUX. 

    with single loop 0-delay mode, should be set to FB_MUX or PLL2_P? Thank you very much.

  • 0 in reply to new2day
    TI__Genius 9460 points

    Hi again,

    In single loop 0-delay mode, PLL2_NCLK_MUX should be set to FB_MUX, so that a phase relationship can be established between PLL2 and the output. 

    Thanks,

    Michael

  • 0 in reply to new2day
    Expert 1950 points

    Hi Michael,

    Thank you very much for your confirmation.

    Unfortunately, I did what's descripted in section 8.3.3.1 after programming Reg 0x000 to 0x555. Which are,

    1. Set 0x139 to 0x00
    2. Set 0x144 to 0x00 or 0x80,
    3. Toggle 0x143 bit[5] LOW-HIGH-LOW
    4. Set 0x144 to 0xFF (back to normal)
    5. Set 0x139 to 0x03 (back to normal

    I've also tried with very long with 0x143 bit[5] = 1 to meet our 1.25MHz SYSREF output.

    I still get phase delta on SYSREF from two LMK04832. 

    Was there any thing more need to be done? Thank you very much.

  • 0 in reply to new2day
    TI__Genius 9460 points

    Did you set the SYNC_EN bit to 1 (bit 4 of 0x143)? That is required to enable the SYNC and SYSREF functionality. 

    Additionally, did you set the SYNC_DISSYSREF bit to 1 (bit 7 of 0x144)? If so, then that could also explain the lack of phase alignment. This bit disables the synchronization upon a SYNC event. 

    Furthermore, the SYNC_MODE bit must be set to 1 to allow for the SYNC_POL bit to generate a SYNC event. 

    Please see section 8.3.2 for more information.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Expert 1950 points

    Hi Michael,

    Appreciate prompt response. 

    I think I did right based what you mentioned above. I'm really confused. 

    1. The SYNC_EN = 1 and the SYNC MODE = 1. (SYNC_MODE = 1 is to use SYNC pin not SPI Pulser) according to the DS.

    These make 0x143 = x"11". Reg 0x143 = 0x31 when set the SYNC_POL HIGH and back to 0x11 when clear it.

    2. About SYNC_DISSYSREF, I've tested with both 1 and 0 corresponding to 0x144 = 0x80 or 0x00.

    See no difference on the SYSREF outputs. 

    3. After toggling SYNC_POL: HIGH then LOW, the SYSREF is set to continuous mode. 

    More updates,

    There is SYNC Dividers button from TICS Pro, by clicking the button, the SYNC process is running with register values. 

    I've copy the registers and values at same sequence. 

    However there is still phase delta between two LMK04832s.

    I think the proper sequences and setting have been done. Really don't what's wrong. 

     

    While waiting for your support, I'll try with the SYNC pin.

    Please see attach TXT file. Which if from you and I put the SYNC Dividers Register writes into it - they are from TICS proc by hit the SYNC dividers button.

    Thank you very much.

    Fullscreen 7485.HexRegisterValues_4832.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D1
R5	0x000563
R6	0x000650
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x01010A
R258	0x010200
R259	0x010344
R260	0x010430
R261	0x010500
R262	0x010601
R263	0x010715
R264	0x010819
R265	0x01090A
R266	0x010A00
R267	0x010B44
R268	0x010C20
R269	0x010D00
R270	0x010E01
R271	0x010F65
R272	0x011019
R273	0x01110A
R274	0x011200
R275	0x011344
R276	0x011420
R277	0x011500
R278	0x011601
R279	0x0117C5
R280	0x011820
R281	0x01190A
R282	0x011A00
R283	0x011B40
R284	0x011C20
R285	0x011D00
R286	0x011E01
R287	0x011FF5
R288	0x012019
R289	0x01210A
R290	0x012200
R291	0x012344
R292	0x012420
R293	0x012500
R294	0x012601
R295	0x012711
R296	0x012810
R297	0x01290A
R298	0x012A00
R299	0x012B40
R300	0x012C20
R301	0x012D00
R302	0x012E01
R303	0x012F11
R304	0x013010
R305	0x01310A
R306	0x013200
R307	0x013340
R308	0x013420
R309	0x013500
R310	0x013601
R311	0x013711
R312	0x013801
R313	0x013903
R314	0x013A07
R315	0x013BD0
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013FA3
R320	0x014081
R321	0x014100
R322	0x014200
R323	0x014319
R324	0x0144FF
R325	0x014500
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014942
R330	0x014A03
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E1E
R351	0x015F13
R352	0x016000
R353	0x016101
R354	0x0162AC
R355	0x016300
R356	0x016400
R357	0x016505
R358	0x016600
R359	0x016700
R361	0x016958
R362	0x016A20
R363	0x016B00
R366	0x016E13
R371	0x017310
R375	0x017700
R386	0x018200
R387	0x018300
R388	0x018480
R389	0x018500
R392	0x018800
R360	0x016801
R1365	0x055500

//-- start SYNC SYSREF --//
//-- from TICS Pro when hit SYNC Dividers button 
014311,
010200,
014480,
010200,
014480,
010A00,
014480,
010A00,
014480,
011200,
014480,
011200,
014480,
011a00,
014480,
011a00,
014480,
012200,
014480,
012200,
014480,
012A00,
014480,
012A00,
014480,
013200,
014480,
013200,
014480,

014400,
013900,


//-- 	Wait for SYNC pin goes HIGH
//--	SYNC PIN = HIGH
//--	Wait for SYNC pin goes LOW
//--	SYNC pin = LOW

//-- put following Reg to normal operation

010C20,
011420,
011C20,
012420,
012C20,
013420,

0144FF,
013903,
000700;

  • 0 in reply to new2day
    TI__Genius 9460 points

    Hi again,

    I am going to close this forum as I am assisting you in another forum.

    Thanks,

    Michael