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LMX2694-EP: Clock with Side lobes are occuring.

Vamsi Akula
Prodigy 25 points
Part Number: LMX2694-EP
Other Parts Discussed in Thread: LMK04832, LMX2694EPEVM

Tool/software:

Hey Sir/Ma'am,

Hope you are doing really well. 

we have one custom design with lmx2694 with it,

with input clock of lmx2694 is 491.52mhz and output desired clock is 5.898ghz at RFoutB port!

clock is generating @ desired centre frequency but side lobes are added to it, which cant be acceptable in design perspective.

registers used and signal picture are both attached below.

hope this issue solves very soon.

thanks in advance!

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R114 0x720000
R113 0x710000
R112 0x700000
R111 0x6F0000
R110 0x6E0000
R109 0x6D0000
R108 0x6C00F1
R107 0x6B0000
R106 0x6A0007
R105 0x694440
R104 0x680000
R103 0x670000
R102 0x660000
R101 0x650000
R100 0x640000
R99 0x630000
R98 0x620000
R97 0x610000
R96 0x600000
R95 0x5F0000
R94 0x5E0000
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0
    TI__Guru* 97310 points

    Hi Vamsi,

    this is an integer channel, there will be no spurs so the lobes you are seeing are not spurs from the synthesizer.

    Can you confirm it is indeed locked? You can confirm this with the MUXOUT set as Lock Detect output and also reading back register R110 rb_LD_VTUNE. 

    Can you also measure the reference clock to see if has similar lobes?

    I believe the reference clock is a differential clock, how did you connect it to the LMX device?

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi Noel sir,

    First of all. Extremely sorry for late response.

    i understood 3 questions from this conversation. ill try to answer all.

    1. Does reference clock also have similar side lobes?
       -> No, reference signal didnot observed any side lobes.


    2. Is reference clock for lmk is differential and how did it connected to lmx?
       -> Yes it is differential, it is coming from a ic called lmk04832.

    3. is rb_LD_VTUNE locked?
        -> Yes it is, checked from reading from MUXOUT (R110[10:9]= 2)(attached picture for reference)

    Looking forward for support sir.

    thanks:)

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    0x0688 means it is unlocked. If it is locked, it should be 0x0488. 

    How did you connect the clock between LMK04832 and LMX2694?

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    My Bad!

    Coming Back to the question!



    Above mentioned is the path from lmk to afe which is coming from CLKOUT12 p and n. and those are feeding to lmx as below mentioned.



    lmk04832 registers are mentioned in code snippet!

    thanks sir!

    Fullscreen
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    R0 0x000090
    R0 0x000010
    R2 0x000200
    R3 0x000306
    R4 0x0004D1
    R5 0x000563
    R6 0x000670
    R12 0x000C51
    R13 0x000D04
    R256 0x010018
    R257 0x01010A
    R258 0x010210
    R259 0x010340
    R260 0x010430
    R261 0x010500
    R262 0x010601
    R263 0x010711
    R264 0x010806
    R265 0x01090A
    R266 0x010AF0
    R267 0x010B40
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to Vamsi Akula
    Prodigy 25 points

    Hi sir,

    Need to add some more information to the form actually. We actually tried to make the lock up with 25MHz reference clock, and got locked status from r110, but side lobes are still existing. video and registers used are mentioned below.

    Fullscreen
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    R114 0x72026F
    R113 0x710001
    R112 0x70012F
    R111 0x6F001F
    R110 0x6E0488
    R109 0x6D9D7D
    R108 0x6C00F2
    R107 0x6B4001
    R106 0x6A0007
    R105 0x694440
    R104 0x680000
    R103 0x670000
    R102 0x660000
    R101 0x650000
    R100 0x640000
    R99 0x630000
    R98 0x620000
    R97 0x610000
    R96 0x600000
    R95 0x5F0000
    R94 0x5E0000
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX



    We also tried to make a setup with LMX2694EPEVM, by giving the 122.88mhz(0Dbm From RF generator) reference clock by oscinp and terminating oscinN and taking the output from RFoutB, Even in this, for some time intervals side lobes are popping, which can see in the video.
    video and registers used are mentioned below for this.


    Fullscreen
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    R114 0x72026F
    R113 0x710001
    R112 0x70012F
    R111 0x6F001F
    R110 0x6E0488
    R109 0x6D9D7D
    R108 0x6C00F2
    R107 0x6B4001
    R106 0x6A0007
    R105 0x694440
    R104 0x680000
    R103 0x670000
    R102 0x660000
    R101 0x650000
    R100 0x640000
    R99 0x630000
    R98 0x620000
    R97 0x610000
    R96 0x600000
    R95 0x5F0000
    R94 0x5E0000
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX


    Hope this information add positive weight to solve this issue sooner sir.

    thanks.

  • 0 in reply to Vamsi Akula
    Prodigy 25 points

    Hi sir,

    To add on more information to it. we tried different set of clock in reference from lmk to lmx. few clock set lock is establishing. That includes, 24.9925423729 mhz, 92.16 mhz, 163.84 mhz. But our desired ref clock in i.e, 491.52mhz is not establishing. But that is fine , we actually can survive on 163.84mhz clock in where lock is establishing. but as i mentioned earlier sir, in that clock in reference also we are seeing the side lobes.

    side lobe delta to main signal picture is mentioned below and r110 read back register also mentioned below.




    thanks.

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    The EVM experiment shown the spurs are not always appear, I strongly believe there is interference in the environment. The configuration is an integer channel, there is no way to generate a 40kHz spurs. Even if the spurs is generated by the synthesizer, the spurs should stay there all the time. I will take some data tomorrow. 

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    Any information or solution you add on to the custom board we made with lmk clock as reference to the lmx. where side lobes are always present in that actually. trace max hold picture is attached previously for reference and used registers and also mentioned previously for both lmk and lmx.

    Any other information you need, plss feel free to ping. we will make sure all the information is given from our side to get solution for this A.S.A.P sir. We stuck in critical timeline actually.

    thanks:)

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    Your configuration in the video is an integer channel but your register dump is a fractional channel. 

    Anyway, I tried both configurations and the result is expected, there is no 40kHz spurs.

    below is the max hold plot.

    Can you test again with another test equipment?

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    we tried with different equipment as well but spurs remained similar. as mentioned below.


    need to add some more information to the forum actually.

    below is the input clock to the lmx from lmk.


    but when we remove the ground connection(from spectrum analyzer) we have seen similar kind of spurs in input clock that is mentioned below.

     

    do you think grounding connection leads to this issue by any chance?

    thanks

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    Looks to me you are using some kind of probe to measure the signal. Is it possible to connect the output of the synthesizer directly to the test equipment?

    Your input clock spurs is about 20dBc, which is too high to be believable. 

    The spurs in the first plot looks like your PLL loop filter phase margin is too small, what is your loop filter bandwidth and phase margin?

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    In our custom board we dont have provision to directly connect the output of lmk04832 to test equipment. But we have the provision of connecting the output of lmx2694 to the test equipment. those snips are already attached in the forum.

    and regarding phase margin and loop filter bandwidth of lmx, may i know where to check that, went through tics pro, but couldnt found that actually.

    thanks.

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    the 5.898GHz signal is -50dBm, this is too small if the LMX2694 output is directly connected to the test equipment. 

    PLL is a close-loop system, loop bandwidth and phase margin represent the characteristic of the loop. 

    What is your loop filter design, phase detector frequency and charge pump current? we need these information to calculate loop bandwidth and phase margin.

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    Above is the picture of lmx evm output with the same registers and clock frequency, this power level also similar, this has nothing to do with probing sir, may be some setting issue in this equipment, previous equipment photos power level seems to be fine. But the main concern is not the power level but the side lobes are still existing when tested on different equipment as well sir.

    We will update you with phase margin and loop filter bw, using platinum sim tool.

    Thanks!

  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    below is the plot I attached previously, output power should be around 5dBm.

  • 0 in reply to Noel Fung
    Prodigy 25 points

    Hi sir,

    After the respective changes in the hardware, we are getting the output without sidelobes, but our major concern still remained sir. 


    Previously lmx is running with loop filter components that are mentioned below.

    Changes to the hardware are done w.r.t the image that mentioned below.

    and we got output which has no sidelobes as mentioned below.
     

    But we are making the lmx2694 up to check the better phase noise meas compared to the lmk04832 while operating with AFE. As we got suggestion that lmx provides better phase noise compared to lmk. but that is not seeming to be fulfilled sir. Below is the table of phase noise of afe(@9.5 gig centre) with lmk, lmx and reference lmx data provided by ti.

    Freq offset(SSB)(ddc/hz)
    AFE with lmk-04832
    AFE with lmx-2694
    TI REF data (AFE WITH LMX)(@9.6gig centre)
    100Hz
    -72.49
    -76.10
    -88
    1Khz
    -92.11
    -94.08
    -99
    10khz
    -101.45
    -102.72
    -109
    100Khz
    -101.20
    -100.91
    -116
    1mhz
    -120.91
    -121.76
    -135
    below is the snippet for phase noise reference table provided by ti in a ppt.

    Hope this information add on to help in better understanding sir.

    thanks,
    Vamsi Akula.



  • 0 in reply to Vamsi Akula
    TI__Guru* 97310 points

    Hi Vamsi,

    With LMX2694 eval board default configuration and a good reference clock, the sim result has better phase noise than your configuration. This is probably due to lower fpd in your configuration.

    Default eval board configuration.

    You can make fpd higher, for example,

    How does the 491.52MHz clock look like? This clock also affect LMX2694 output phase noise.