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CDCE913: Calculating PLL register settings without ClockPro

Wolfgang R.
Intellectual 386 points

Part Number: CDCE913
Other Parts Discussed in Thread: CLOCKPRO

Tool/software:

Hi all,

we plan to use CDCE913 in a redesign to replace a discontinued part.
It is used as main clock source for a C2000 microcontroller.

The requirement is to provide any frequency between 19.0 and 20.0 MHz with 5 kHz step width, and to switch between 2 arbitrary frequencies in this range at a rate of up to 50 Hz without glitches or frequency overshoot.
PLL Clock source is a 20 MHz XTAL. The CDCE913 seems fine for this.

However, we do not know the required frequencies in advance, i.e. we have to calculate the PLL register settings "on the fly" in the microcontroller. Hence, we cannot use TI ClockPro to precalculate the register data.

With the information in the datasheet we can calculate N, P, Q, R and Pdiv register data for given Pdiv, N and M.

But for most frequencies there are multiple combinations of Pdiv, N, M that lead to the desired output. Which to chose?
Question 1: is there a document describing how to chose Pdiv, N, M for given fIn and fOut?

Question 2: Will all possible combinations of Pdiv, N, M work, as long as these constraints are met:


Our approach is now as follows:
Use fixed values Pdiv1 = 8 and M = 500 and vary N from 3800 to 4000 to get 19.0 to 20.0 MHz output in even 5 kHz steps.
fVCO runs at 152 to 160 MHz in 40 kHz increments.
Question 3: Will this work?

I tried TI ClockPro for some frequencies to compare the results with our approach.
ClockPro seems to try to maximize Pdiv, maybe to improve jitter performance, leading to different results than with our simple approach.

  • +1
    TI__Mastermind 23280 points

    Wolfgang,

    1. The description for selecting the values of N, M, and PDIV found in 8.2.2.2 PLL Frequency Planning is what we have. P, Q, and R are determined as follows


      In general, the values of N and M should be maximized for best performance. For example, if you were to generate 10MHz and 15MHz from a 20MHz input, then instead of selecting M = 1 and N = 21, the recommendation is to use M = 390 and N = 4095.
    2. There are not gaps in the range of Pdiv, N, and M values. Any combination that is valid will work on the device.
    3. I see no issue with the approach that you are using. It will be simpler and require less register writes, although the performance may be worse for some output frequencies compared to maximizing M/N. This may not be an issue for your system depending on your requirements, and will greatly simplify the math.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Intellectual 386 points

    Hi Kadeem,

    Thanks for your quick response confirming our approach.

    2 Notes:

    Constrint 0 <= R <= 51 in the datasheet (see your snippet above) seems incorrect, it should be r <= 511; I already fixed this in the constraints snippet I posted, it's from the same source. The same the 2 other datasheets of this device family, only one has 511 (I can't recall which, though).

    You mentioned maximizing M and N for better performance - ClockPro does not seem to follow this strategy.
    Example for fIN 20 MHz, fOUT 19.020000 MHz
    ClockPro: Pdiv=12, N=2853, M=250, fVCO=228.24 MHz
    ours: Pdiv=8, N=3804, M=500, fVCO=152.16 MHz
    So we have in fact larger values for M and N, but smaller Pdiv than ClockPro
    Maybe ClockPro attempts to maximize Pdiv (and thus also fVCO) to reduce jitter.
    Anyway, we won't care :-)

    Regards,
    Wolfgang

  • 0 in reply to Wolfgang R.
    TI__Mastermind 23280 points

    Wolfgang,

    This is a typo in the datasheet, the max R value is 511 (9 bit field). 

    For maximization of values, this is explicitly with regard to M and N. My apologies for the lack of clarity.

    Thanks,

    Kadeem