• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 198 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMX2572: Phase synchronization can not be achieved

LMX2572: Cannot sync RF outputs with SYNC line

David
Prodigy 10 points
Part Number: LMX2572LP

Tool/software: TI TICS PRO 1.7.7.6

I have 2 boards each with a LMX2572LP. Both are supplied with an identical 10Mhz input clock, and both are connected to one TI Reference Pro board, and both are programmed to output 200Mhz. Both are also supplied with an identical SYNC signal, which is 0 - 3V, on time of 733us, and period of 3 seconds. I'm able to program both parts simultaneously and see the 200Mhz output signals without issue. However, the SYNC functionality doesn't seem to work properly at all. I'm able to see both generators startup and run with random phase differences by toggling the POWERDOWN and/or reset bit in register R0, as expected, but the SYNC signal will either do nothing at all, or will create what seems like 1 of about 10 phase differences between the two signals every time it occurs (in this case every 3 seconds). 1 of those phase relationships is what I'm looking for--the two signals at the same phase--but it only happens randomly and occasionally. The settings I am using are shown below.

I have played around with MASH_RST_COUNT as well as all the other registers, but nothing I've tried seems to fix the issue--I can definitely make it worse, but not better.  

(All my cables and traces are very tightly length and impedance matched, so I don't think that's an issue. )

Any help would be VERY appreciated! 

  • 0
    Prodigy 10 points

    This is a dump of all the register settings I have now:

    Fullscreen
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    R125 0x7D0820
    R124 0x7C0000
    R123 0x7B0000
    R122 0x7A0000
    R121 0x790000
    R120 0x780000
    R119 0x770000
    R118 0x760000
    R117 0x750000
    R116 0x740000
    R115 0x730000
    R114 0x727802
    R113 0x710000
    R112 0x700000
    R111 0x6F0000
    R110 0x6E0000
    R109 0x6D0000
    R108 0x6C0000
    R107 0x6B0000
    R106 0x6A0007
    R105 0x694440
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • 0 in reply to David
    TI__Guru* 97310 points

    Hi David,

    This is a Cat.2 sync, you only need to keep VCO_PHASE_SYNC_EN = 1 all the time, then after programming, all devices will phase align. 

    I see in your configuration, PLL_DEN = 1 while you have enabled MASH_SEED and have a value greater than 1. This is not a valid configuration. I think MASH_SEED is making the trouble to you. 

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel, Thanks for your reply!

    I've tried disabling the MASH_SEED_EN, as well as setting it to 0, but this makes no difference. I have also tried setting the fractional denominator to 0, to 10000, and no change. When I pull the devices out of reset and write all registers they come up with random phases. 

  • 0 in reply to David
    TI__Guru* 97310 points

    Hi David,

    Is your 10MHz sine wave? Can you try with a square wave clock?

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel, I have been using a sine wave, but I just tried it with a 10Mhz 50% square wave and am getting exactly the same results. I also just tried it with a 5Mhz input square, both with and without the input doubler enabled, and same results. I've also tried varying the amplitude of the input clock and the only change I see is when it is too low and lock doesn't occur. 

    (Also, its worth mentioning that in between changes (input signal or register settings), I always reset both chips through the General Controls->Reset command, and then run the write all registers command. I can always see both outputs turn off when I issue the reset command, and then they come back up with random phases after writing all registers. I have both boards connected in parallel to one TI Ref Pro board (USB-SPI converter). 

  • 0 in reply to David
    TI__Guru* 97310 points

    Hi David,

    I think the RESET operation is causing the issue.

    This is actually a TICS Pro problem, not device problem.

    in TICS Pro, after programing RESET = 1. Do the following before de-assert the RESET.

    - in the menu bar, click Options, then uncheck AutoUpdate

    - Set RESET = 0 (this will not program the device)

    - again in the menu bar, click Options, then check AutoUpdate

    - Ctrl+L to program all registers

  • 0 in reply to Noel Fung
    Prodigy 10 points

    Hi Noel,

    From a quick test following your procedure, this does seem to make a difference, and I'm not able to reproduce the phase jumping every time I issue a SYNC signal.   But why??????

    in TICS Pro, after programing RESET = 1. Do the following before de-assert the RESET.   Register 00 is set to 601E

    - in the menu bar, click Options, then uncheck AutoUpdate          Nothing programmed

    - Set RESET = 0 (this will not program the device)         Nothing programmed

    - again in the menu bar, click Options, then check AutoUpdate     Nothing programmed

    - Ctrl+L to program all registers      All registers programmed, ending with reg 00 set to 601C

    Versus what I was doing previously:

    -Auto update on

    -Set RESET = 1.   Register 00 is set to 601E

    -Set RESET = 0.   Register 00 is set to 601C

    -program all registers   All registers programmed, ending with reg 00 set to 601C

    -and the phase now jumps around on nearly every SYNC pulse

     

    In all cases, the only value difference for Reg 00 is the RESET bit. 

    I won't say its solved just yet, since we'll have to test more (most notably using 2 separate USB_SPI converters), but this is looking hopeful. Thanks!