LMK5B33216EVM: DPLL3 No Input selected. LOPL/LOFL Status, no holdover.

Thomas Gayagoy

Part Number: LMK5B33216EVM
Other Parts Discussed in Thread: LMK5B33216, LMK5C33216A

Tool/software:

Hello,

We are using the LMK5B33216 Evaluation board with the default TCXO (48MHz) with a single-ended 125 MHz input connected to IN0_P (J4). It looks like we have the DPLL settings setup to where it is choosing the right reference and not auto-reverting to the holdover setting. We are still seeing a message on the input page saying "No input selected" and the status page is showing loss of lock for DPLL3. Is there anything we are missing with our configuration? We are measuring an output on OUT0 at 25 MHz but we are not sure if we are somehow using the XO reference instead of the selected input clock reference.

Attached are some screenshots and the configuration file.

Thank you for the help,

Tom

LMK5B_tics_pro_v6_4G.tcs

8 months ago

0 Jennifer Bernal 8 months ago

TI__Genius 16615 points

Hi Thomas,

I can check your configuration file tomorrow.

In the meantime, please review the following videos to make sure the TICS Pro GUI settings are configured properly.

Video - TICS Pro LMK5Bxxxxx and LMK5CxxxxxxA profile overview
1. Contains page-by-page description of the TICS Pro profiles for LMK5B33216/LMK5C33216A
2. https://www.ti.com/video/6358429135112
Video - TICS Pro LMK5B/LMK5C start page tutorial
1. Contains the step-by-step instructions of the TICS Pro Start Page for configuring LMK5B33216/LMK5C33216A
2. https://www.ti.com/video/6362731785112

Regards,

Jennifer

0 Jennifer Bernal 8 months ago in reply to Jennifer Bernal

TI__Genius 16615 points

Hi Thomas,

The default EVM setting is using the 48MHz TCXO output for the XO input of the LMK5B33216. The IN0 and IN1 pins are not routed to a signal by default and require external connection by the user (the 125MHz input signal).

I couldn't get the DPLL to lock with your config. Please make sure to follow the instructions from the above video links.

Here is a config with DPLL lock:e2e_LMK5B33216_REF=125MHz_XO=48MHz.tcs.

Let me know if this helps or if you have further questions!

Regards,

Jennifer

0 Thomas Gayagoy 7 months ago in reply to Jennifer Bernal

Prodigy 75 points

Hi Jennifer,

We managed to get rid of one of the loss of lock signals just by waiting a few minutes. Some adjustments to the validation page allowed us to clear both loss of lock signals.

Thanks for the help,

Tom

0 Jennifer Bernal 7 months ago in reply to Thomas Gayagoy

TI__Genius 16615 points

Hi Tom,

Thanks for the update. I will close this ticket. If you have further questions, please create a new thread.

Regards,

Jennifer

Clock & timing

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LMK5B33216EVM: DPLL3 No Input selected. LOPL/LOFL Status, no holdover.