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CDCE62005 non constant skew after SYNC

stephane detraz
Prodigy 60 points
Other Parts Discussed in Thread: CDCE62005

Dear all,

 

I would like to point out that we have observed a non-constant skew of the CDCE62005 after a SYNC.

In this post skew refers to the phase between the CDCE62005 input clock (its reference clock) and its output clock(s).

In our application a constant skew is mandatory and we have chosen the CDCE62005 because of its capacity to synchronise the output dividers with the reference clock using the SYNC signal.

Concerning the SYNC signal we have used the following setting:

 

R4.1=1 (“outputs have deterministic delay relative to low-to-high pulse of SYNC pin when the SYNC

signal is synchronized with the reference input”).

R6.20=0 (“when set to "0", outputs are synchronized to the reference input on the low-to-high pulse EEPROM on SYNC pin or bit”).

 

We have produced 25 boards using this component. Because we have found out this non-constant skew we have extensively tested these boards. The test consists in generating multiple SYNC sequences and measuring the skew on an oscilloscope. We have also observed ambient temperature dependency. Thus we have done this test for 2 different temperatures (10C & 35C). The number of cycles for each temperature was 500.

 

We have found 12 boards (thus 12 CDCE62005) with a non-conform behaviour (at least non-conform for our application). Indeed for these components the skew was changing between 2 different values separated by around 1ns (which corresponds to the clock period after the prescaler).

This variation happens on some boards very rarely (e.g. 2 times for 500 cycles) but on other boards much more frequently (e.g. 238 times for 500 cycles) and the phenomena depends on the ambient temperature. For some components it never happens (at least for 500 cycles) at 35C but we can observe the variation at 10C (but this is also right in the opposite direction for other components).

 

Could you tell us if this behaviour is normal and/or known by TI or do you have any clue of what we could have done wrong?

 

Cheers,

 

Stéphane

 

  • 0
    TI__Expert 4150 points

    Hello Stephane,

    I am sorry, this must be a very frustruting to experience. Unfortunately the device must first "sample" the external sync pulse. You properly gate the pulse with the input sync signal. Device internal, the output needs to be syncronized to the pre-scaler clock. Therefore, a second sampling stage syncronizes the (now internal) sync pulse with the pre-scaler clock. The pre-scaler clock and the input clock are undetermined in their phase relationship. Thus, one pre-scaler cycle uncertainty will remain. 

    The total phase uncertainty of one pre-scaler clock cycle (in your case 1ns) will always be present and show up on every IC over temperature and different settings. For a relative slow input reference clock (e.g. 10MHz clock with 100ns clock cycle) the syncronization feature reduces the uncertainty to 1% (e.g. 1ns in your case) but can not remove it.

    The only thing you can do is is to minimize the pre-divider, to make the timing error due to the pre-scaler clock cycle as small as possible. It seems like you already did this as well.

     

    Best regards. Fritz

     

  • 0 in reply to Fritz
    Prodigy 60 points

    Hello Fritz,

    What did you mean by "properly gate the pulse with the input sync signal"? I am using the option to synchronise the SYNC pulse with the reference clock internally (R6.20=0).

    In this case, I suppose I do not need to synchronise the SYNC pulse externally. By the way, I have tried to do so using a D latch flip-flop. This flip-flop latches the SYNC signal to the input (reference clock) before feeding it to the CDCE62005. I haven’t observed any change with the previous CDCE configuration (R4.1=1,R6.20=0). But I have done the test again (using this external flip-flop) with no INTERNAL synchronisation to the reference clock (R4.1=1, R6.20=1).  With this last configuration the skew was stable (over several thousand synchronisation cycles) for the full temperature range (from 5C to 40C).  This test has been done using a CDCE which was very “unstable” (238 skew changes over 500 cycles @ 10C with no external flip flop).

    Apart from that I do not fully understand why using an external latch can give such better results than using the internal one. I would like your opinion about this solution. I guess it will not guarantee a constant skew in any case?

    If a constant skew (better than +/-100ps) could not be guaranty with the CDCE62005, do you have any other component that could do the job?

    TI bought National Semiconductor and I found the LMK04800 that looks promising. Could you give information about this component (or the two company portfolios are still separated)?

    Thank you for your help.

    Best regards.

    Stéphane