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LMK04832: LMK04832 CML Output [DC Termination Versus AC Termination

Part Number: LMK04832

Tool/software:

I'm using the LMK04832 in Dual Loop Mode.

1. PLL1 Reference is 100MHz

2. PLL2 Reference is 156.25MHz External VCXO [Fed into OSCin]

3. PLL1 R = 16, PLL1 N = 25

4. Goal is run PLL2's Internal VCO [VCO1] @ 1.611328125GHz

5. PLL2 R = 8, PLL2 Pre-N = 5, PLL2 N = 33

I want to Configure the {2} Output Clocks as CML 32mA.

Question-1: Can these Output Clocks, running at 1.611328125GHz, configured as CML 32mA, come from "Even" Clock Output Pins or "Odd" Clock Output Pins?

A). DC Termination Analysis

1. Vod = 1660mV [Termination 50Ohm Pull-Up to Vcc]

When QB = "Off", QA = "On"

  • VA = +3.3V
  • 32mA flows through 50Ohm Resistor [External Rb] setting VB = 3.3V - [(50Ohm) * (32mA)] = 3.3V - 1.6V = 1.7V

When QB = "On", QA = "Off"

  • VB = +3.3V
  • 32mA flows through 50Ohm Resistor [External Ra] setting VA = 3.3V - [(50Ohm) * (32mA)] = 3.3V - 1.6V = 1.7V

Vod = 1.6V [Data Sheet says 1600mV]; I'm Good with this Calculation!

2. Vod = 1070mV [Termination 50Ohm Pull-Up to Vcc, AC-Coupled with 100Ohm Termination at the Load-Side]

When QB = "Off", QA = "On"

  • VA = +3.3V
  • 32mA flows through 50Ohm Resistor [External Rb] in "Parallel" with Load [Load = 100Ohm] setting VB = 3.3V - [(50Ohm || 100Ohm) * (32mA)] = 2.233V

When QB = "On", QA = "Off"

  • VB = +3.3V
  • 32mA flows through 50Ohm Resistor [External Ra] in "Parallel" with Load [Load = 100Ohm] setting VB = 3.3V - [(50Ohm || 100Ohm) * (32mA)] = 2.233V

Vod = 1.0667V [Data Sheet says 1070mV]; I'm Good with this Calculation!

B). AC Termination Analysis

1. Vod = 550mV to 765mV [DC Biased is 68nH to 20Ohm to Vcc, AC-Coupled with 100Ohm Termination at the Load-Side]

Z {Inductor} @ 0GHz = j * Omega * L = j * 2 * Pi * 0GHz * 68nH = j0 Ohms [@ D.C.]

Z {Inductor} @ 2.5GHz = j * Omega * L = j * 2 * Pi * 2.5GHz * 68nH = j1068 Ohms [@ 2.5GHz]

When QB = "Off", QA = "On"

  • VA = +3.3V
  • 32mA flows through 20Ohm + 68nH Inductor which is in Parallel with the Load [100Ohms] setting VB = 3.3V - [(20Ohm + J1068) || 100Ohm) * (32mA)]

I must be making some sort of Math Error, because when I try to solve this equation, I don't get Vod = 765mV [IDL = 1] or Vod = 550mV [ODL = 1]

Question-2: Could you Outline the Math Steps to get VB = 3.3V - [(20Ohm + j1068) || 100Ohm] *32mA = 2.535V [Vod = 765mV] or VB = 3.3V - [(20Ohm + j1068) || 100Ohm] *32mA = 2.75V [Vod = 550mV]?

  • Hi Dallas,

    Question-1: Can these Output Clocks, running at 1.611328125GHz, configured as CML 32mA, come from "Even" Clock Output Pins or "Odd" Clock Output Pins?

    Using CML as an output format requires bypass mode, meaning the output dividers cannot be used. Furthermore, only the even clock output pins may output using CML. As a result, 3.22265625 GHz may be output, but only by CLKout0/2/4...

    Question-2: Could you Outline the Math Steps to get VB = 3.3V - [(20Ohm + j1068) || 100Ohm] *32mA = 2.535V [Vod = 765mV] or VB = 3.3V - [(20Ohm + j1068) || 100Ohm] *32mA = 2.75V [Vod = 550mV]?

    I will keep working to verify this calculation for you. For now, I can tell you that I am not certain that the effective load in parallel with the RL combination is 100 Ohms - at least not for the IDL = 1 case. For the ODL = 1 case, that should be close to the effective load. 

    Thanks,

    Michael

  • Question: Have you been able to determine Vod with 20Ohms in Series with 68nH Pulled Up to +3.3V, AC-Coupled to 100Ohm?

    1. For the DC Termination Case, the "Math" works [50Ohm Pulled Up to +3.3V in Parallel with 100Ohms]:

    A). DC bias is 50Ohm pull up to Vcc {3.3V}, AC-Coupled to RL = 100Ohm

    When QB = "On", QA = "Off"

    • VA = +3.3V
    • 32mA flows through 50Ohm Resistor [External Rb] in "Parallel" with Load [Load = 100Ohm] setting VB = 3.3V - [(50Ohm || 100Ohm) * (32mA)] = 2.233V

    Vod = 1.0667V [This "Agrees" with the Data Sheet Vod = 1070mV]

    2. For the AC Termination Case [@ 2.5GHz]

    If I replace the 50Ohm Pull-Up with 20Ohm in Series with 68nH, I get:

  • Hi Dallas, 

    I will get to your question next week.

    Thanks,

    Michael