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LMK04828: PLL2 DLD Edge falls

Etienne Drouin
Prodigy 70 points
Part Number: LMK04828
Other Parts Discussed in Thread: ADC08DJ3200, ADC08DJ3200EVM, LMX2582,

Tool/software:

Hi everyone,

I have a design similar to the ADC08DJ3200EVM with an ADC08DJ3200, a LMK0828 and a LMX2582. The design works on a lot of the boards but doesn't work on a few of them. When I read back the registers on those chips, the only obvious change is the register 0x183 on the LMK that has the value 04 on the non working board instead of 0 on the working one. The register definition says that it means PLL2 DLD edge falls. I guess that mean the PLL is not stable and going in and out of lock, but what can I do to diagnose those board that don't work?

Regards,

Étienne Drouin

  • 0
    TI__Genius 12140 points

    Hi Étienne,

    Would you be able to provide a schematic or block diagram? 

    As you stated, PLL2 has lost lock. The fact that PLL1 did not lose lock tells me that the input signal is valid and the XO is working. However, it is a bit concerning that PLL2 is not locking. Generally, that should be able to lock, even without a valid reference signal. Would it be possible for you to share the clock tree, as well as the configuration file for the LMK04828 (preferably as a .tcs file, but a hex file will also work).

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 70 points

    Hi,

    We don't really use .tcs file. I used the ADC12DJxx00 GUI to configure everything and that gives a .cfg. I tried to create some hex files using TCIS pro, tell me if that help you. I don't really know what you are looking for when asking for a clocking tree, we have one clock going from the LMX to the LMK and one clock from the LMK going to the ADC.

    Étienne

    Fullscreen HexRegisterValuesLMK.txt Download 
    R0 (INIT)	0x000090
R0	0x000080
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010010
R257	0x010155
R258	0x010255
R259	0x010300
R260	0x010420
R261	0x010500
R262	0x0106F0
R263	0x010711
R264	0x010801
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF9
R271	0x010F00
R272	0x01100A
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011402
R277	0x011500
R278	0x0116F8
R279	0x011700
R280	0x01180A
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C02
R285	0x011D00
R286	0x011EF8
R287	0x011F00
R288	0x012010
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012422
R293	0x012500
R294	0x0126F0
R295	0x012701
R296	0x01280A
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F05
R304	0x013010
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013422
R309	0x013500
R310	0x0136F0
R311	0x013701
R312	0x013845
R313	0x013903
R314	0x013A00
R315	0x013BA0
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x014000
R321	0x014100
R322	0x014208
R323	0x014311
R324	0x0144FF
R325	0x014500
R326	0x014618
R327	0x014702
R328	0x014802
R329	0x014902
R330	0x014A33
R331	0x014B02
R332	0x014C00
R333	0x014D00
R334	0x014E00
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01540C
R341	0x015500
R342	0x01560C
R343	0x015700
R344	0x015878
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F13
R352	0x016000
R353	0x016102
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016801
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E04
R371	0x017360
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
    Fullscreen HexRegisterValuesLMX.txt Download 
    R70	0x460000
R69	0x450000
R68	0x440089
R64	0x4000AF
R62	0x3E0040
R61	0x3D0001
R59	0x3B0002
R48	0x3003FC
R47	0x2F00CF
R46	0x2E0F37
R45	0x2D0000
R44	0x2C0000
R43	0x2B0000
R42	0x2A0000
R41	0x2903E8
R40	0x280000
R39	0x278204
R38	0x260040
R37	0x254000
R36	0x240C10
R35	0x23019B
R34	0x22C3F0
R33	0x214210
R32	0x204210
R31	0x1F0601
R30	0x1E0034
R29	0x1D0084
R28	0x1C2924
R25	0x190000
R24	0x180D09
R23	0x178842
R22	0x162300
R20	0x140064
R19	0x130965
R14	0x0E018C
R13	0x0D4000
R12	0x0C7001
R11	0x0B0018
R10	0x0A10D8
R9	0x090302
R8	0x081084
R7	0x0728B2
R4	0x041943
R2	0x020500
R1	0x01080B
R0	0x002218
    cfg_6400GSample_Jmode5_3.cfg

  • 0 in reply to Etienne Drouin
    TI__Mastermind 29942 points

    Hi Etienne, 
    We would need a high level block diagram or a schematic to better understand how these devices are connected. 

    How is STATUS_LD2 configured? If it's still configured as PLL2 lock detect this pin must be low. 
    As Michael mentioned normally PLL2 will always lock and the issue is usually PLL1. 
    Refer to this post for Mouser as to what we mean by a clock tree: https://www.mouser.com/pdfdocs/clock-tree-101-timing-basics.pdf?srsltid=AfmBOopPIP73EfPZf_orwc2hviFKawRamns5KmSmBptypqh_Iccs9osk

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    TI__Mastermind 29942 points

    Hi Etienne, 
    After reviewing your schematic, I have a better idea of how these devices are connected. 
    Given the reference comes from the LMX part - when the LMK04828 is unlocked do you know what the state of the reference clock is? 
    Is the LMX part also unlocked? 
    The LMX part outputs CML and is an open collector which requires an external pull up to VDD which you do have. 

    If you're 100% certain the LMX output clk being used as reference to LMK04828 is always valid - I would start suspecting the VCXO. 

    Best regards, 

    Vicente