Tool/software:
I am interested in using the LMK05028 (or something similar) to drive the clock of the AM263P4AC using the recovered clock from the DP83869 PHY. However, I am a bit confused on how to connect the CLK_OUT of the DP83869 (which is 3.3V logic) to the input of the LMK05028 because the differential swing can only be 2V? Do you recommend a level shifter for the recovered clock or to have a ref voltage at the INX_N input of the LMK05028?
Here is a simplified block diagram of my system
I am also open to other PLL chips if they are better suited for this application
Hi Shivani,
If LVCMOS 3,3V, it is fine to connect directly to IN0_P since it can take LVCMOS. Terminated INx_N to GND.
If CLK_OUT is in differential format, the peak-to-peak swing is 2V max. You can terminate the circuit to reduce the swing and do AC-coupling.
Best,
Riley
but if you send 3.3V into IN0_P and INx_N is GND, then the Vdiff will be 3.3V and therefore out of range. I did find the information on this though and seems I should just add a simple voltage divider