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LMK05318BEVM: DPLL Phase Lock Detecter Parameter

Zain Alishammat
Prodigy 220 points
Part Number: LMK05318BEVM
Other Parts Discussed in Thread: LMK05318B

Tool/software:

Hello,

I have LMK05318BEVM und it works very well. 

I have been able to synchronise a 100 MHz output frequency to 1 KHz input frequency (phase and frequency) with the following thresholds paramters set in TICS Pro:

  1. For DPLL Phase Lock Detect:
    1. Lock thresh 7.59 ns
    2. Unlk thresh 484.45 ns
  1. For DPLL frequency Lock Detect:
    1. Accurcy 1 ppm

These thresholds are the maximum I could set depending on the input frequency. I found this out by simply testing several values. For example, when i set Unlk thresh under 484.45 ns the phase is no more locked. I check this using flags with the status0 led.
The thing is, according to the oscilloscope I get a phase offset between input and output within 5 ns max. But according to the parameters of the DPLL Phase Lock Detecter, the phase offset is almost 400 ns. The DPLL is considered to be phase locked if the phase difference between the two inputs of the TDC (divided reference and divided VCO1) is within the lock threshold. TDC frequency is 1 kHz because R devider is set to 1

I am confused. Who can help?

BR

Zain

  • 0
    TI__Expert 3135 points

    Hi Zain,

    Could you share tcs file?

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 220 points

    hi Riley,

     

    i

  • 0 in reply to Zain Alishammat
    TI__Expert 3135 points

    Hi Zain,

    Thanks for the file. I will check on this and get back to you.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 220 points

    Hi Riley,

    do you have any new info?

    I can'nt really get the phase locked preciselly. On the Osci i have allways 300 us offset and in the TICS Pro i can'nt set DPLL Phase Lock Detect "Unlk thresh" under 485,45 ns". When i do this the phase is unlocked.

    BR

    Zain

  • 0 in reply to Zain Alishammat
    TI__Expert 3135 points

    Hi Zain,

    For 1kHz input, TI recommends to start with 1PPS default config and changing the input and output for the system needs.

    The 1PPS default config has pre-set registers for low frequency input. The DPLL LBW is recommended is 1 Hz or 10 Hz for 1 kHz input.

    For DPLL lock, it is important to have input validated: xxxREF_VALSTAT = 1. Please try this config:

     1kHz REF, LBW 1Hz_100hz-100MHz.tcs

    If you're using single ended on P side of the input reference, ensure to have 50 Ohm termination on N side.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 220 points

    Hi Rieley,

    The problem was solved. It was solely due to the PLL LBW being set too high, namely 100. I experimented myself and came up with a value of 14. In any case, it is the best so far and with a phase offset of 3 ns and phase lock time of 3.2 s.

    the problem but I can not confirm it via the oscilloscope. So far i confirmed the lock time over the DPLL Phase Lock Detect. The oscilloscope shows a phase offset of 203 us. and when i soft reset the chip it changes a little bit

    Like why?

    Thank you Riley

    BR

    Zain

  • 0 in reply to Zain Alishammat
    TI__Expert 3135 points

    Hi Zain,

    Sorry for the typo in LBW, I meant to use 1 Hz or 10 Hz for 1 kHz input. Good to hear that it's working on your end.

    Can you elaborate a bit more on the test of phase offset and lock time? What are you trying to achieve here?

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 220 points

    Hi Riley,

    if i want to check the phase offset in the oscilloscope, i get 203 or sometimes 300 us offset. But in the TICS Pro i set the DPLL Phase Lock Detect to unlock if the offset over 3.2 ns. And it works very well. But it is possible that the offset in the oscilloscope is not matched to that in the  TICS Pro?

    Did i miss something here?

    Should not the phase offset in the TICS Pro matche the one in the oscilloscope?

    Every time i make an soft reset i get another phase offset. But all of them are too big in us scale.

    BR

    Zain

  • 0 in reply to Zain Alishammat
    TI__Expert 3135 points

    Hi Zain,

    I think you are referring to different things here.

    The phase offset measured on oscope is between input and output - it would be random on each reset due to the output divider.

    DPLL Phase Lock Detect is different from phase offset between input - output. The lock and unlock threshold refers to TDC error of DPLL between input clock and DPLL FB clock from VCO. DPLL flags lock when the TDC error falls in the DPLL frequency and phase lock threshold.

    -Riley

  • 0 in reply to Riley Nguyen
    Prodigy 220 points

    Hi Riley,

    Riley Nguyen said:
    The lock and unlock threshold refers to TDC error of DPLL between input clock and DPLL FB clock from VCO. DPLL flags lock when the TDC error falls in the DPLL frequency and phase lock threshold.

    But this means the phase offset (the measured TDC error) falls between the threshold values!!

    Yes, it's actually random at every reset.

    But where is the phase synchronization? In the datasheet of  LMK05318B is mentioned "The LMK05318B is high-performance network synchronizer clock device" and is is compatible to "IEEE 1588 PTP Slave Clock". The IEEE 1588 PTP Slave Clock requires phase offset  < 10 ns

    Whatever is meant here, whether it's an output divider or not, the output must be synchronized with the input. That's all this chip ever distinguishs.

    I can't imagine the offset being in the us range. And upon all it is also random!!

    How to achieve phase synchronization in the nanosecond range?

    Is that even possible?

    BR

    Zain

  • 0 in reply to Zain Alishammat
    TI__Expert 3135 points

    Hi Zain,

    For synchronization, try enable a SYNC on both VCO dividers and output dividers:

    - PLL1_P1_SYNC_EN = 1

    - CH0_1_SYNC_EN = 1

    - CH7_SYNC_EN = 1

    - Assert sync by toggling SYNC_SW = 1 -> 0

    -Riley