LMK05318BEVM: DPLL Phase Lock Detecter Parameter

Hi Zain,

Could you share tcs file?

-Riley

hi Riley,

https://drive.google.com/file/d/1oYBJZ6HX50RwuR0wIN8D3neBQAjhP4SZ/view?usp=drive_link

i

Hi Zain,

Thanks for the file. I will check on this and get back to you.

-Riley

Hi Riley,

do you have any new info?

I can'nt really get the phase locked preciselly. On the Osci i have allways 300 us offset and in the TICS Pro i can'nt set DPLL Phase Lock Detect "Unlk thresh" under 485,45 ns". When i do this the phase is unlocked.

BR

Zain

Hi Rieley,

The problem was solved. It was solely due to the PLL LBW being set too high, namely 100. I experimented myself and came up with a value of 14. In any case, it is the best so far and with a phase offset of 3 ns and phase lock time of 3.2 s.

the problem but I can not confirm it via the oscilloscope. So far i confirmed the lock time over the DPLL Phase Lock Detect. The oscilloscope shows a phase offset of 203 us. and when i soft reset the chip it changes a little bit

Like why?

Thank you Riley

BR

Zain

Hi Zain,

Sorry for the typo in LBW, I meant to use 1 Hz or 10 Hz for 1 kHz input. Good to hear that it's working on your end.

Can you elaborate a bit more on the test of phase offset and lock time? What are you trying to achieve here?

-Riley

Hi Riley,

if i want to check the phase offset in the oscilloscope, i get 203 or sometimes 300 us offset. But in the TICS Pro i set the DPLL Phase Lock Detect to unlock if the offset over 3.2 ns. And it works very well. But it is possible that the offset in the oscilloscope is not matched to that in the  TICS Pro?

Did i miss something here?

Should not the phase offset in the TICS Pro matche the one in the oscilloscope?

Every time i make an soft reset i get another phase offset. But all of them are too big in us scale.

BR

Zain

Hi Riley,

Riley Nguyen said:

The lock and unlock threshold refers to TDC error of DPLL between input clock and DPLL FB clock from VCO. DPLL flags lock when the TDC error falls in the DPLL frequency and phase lock threshold.

But this means the phase offset (the measured TDC error) falls between the threshold values!!

Yes, it's actually random at every reset.

But where is the phase synchronization? In the datasheet of  LMK05318B is mentioned "The LMK05318B is high-performance network synchronizer clock device" and is is compatible to "IEEE 1588 PTP Slave Clock". The IEEE 1588 PTP Slave Clock requires phase offset  < 10 ns

Whatever is meant here, whether it's an output divider or not, the output must be synchronized with the input. That's all this chip ever distinguishs.

I can't imagine the offset being in the us range. And upon all it is also random!!

How to achieve phase synchronization in the nanosecond range?

Is that even possible?

BR

Zain

Hi Zain,

For synchronization, try enable a SYNC on both VCO dividers and output dividers:

- PLL1_P1_SYNC_EN = 1

- CH0_1_SYNC_EN = 1

- CH7_SYNC_EN = 1

- Assert sync by toggling SYNC_SW = 1 -> 0

-Riley