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LMK05318BEVM: Lock detection issue when no local reference

Nir Alon
Intellectual 600 points
Part Number: LMK05318BEVM
Other Parts Discussed in Thread: LMK05318B

Hello all,

I was just finishing evaluate the LMK05318B when I came across this issue:

I'm using STATUS0 & STATUS1 as an lock detection indicators for ALL2 and DPLL (I use DPLL Mode With Cascaded APLL2)

STATUS0 is set for - DPLL Phase Lock Detection

STATUS1 is set for - PLL2 Digital Lock Detect

Step 1: Both D4 and D5 LEDs are on (indicating both PLLs are locked)

Step 2: I've removed jumper J9 (local XO VCC) to simulate a malfunction and indeed both LEDs turned off.

Step 3: Reinserting J9 brought me back to step 1, as expected.

Step 4: Removing external reference, D4 (DPLL indicator) turned off, and then back on when reconnecting external reference, as expected.

Until now, every indicator is working just fine, until I repeated all steps when the EVM power is off and then turned on:

Step 5: EVM is off, J9 is removed, external reference is on. 

Step 6: EVM is turned on, D5 (APLL2 indicator) is ON, when it shouldn't because there is no 48.0048MHz reference presence.

Step 7: Reinserting J9 and D5 remained ON

Step 8: Removing J9 and D5 turned OFF (back to normal operation)

In short, there is a false indication of ALPP2 digital lock detection when powering on the chip with no local reference.

I've found this post, describing almost the same issue, but with a different PLL:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1116391/lmx2595-lock-detect-reports-sporadic-false-lock-when-refin-removed/4143089#4143089

Is there a way to workaround this issue? (I'm not using any system host in my design)

Thanks,

Nir

  • 0
    TI__Genius 12925 points

    Hi Nir,

    Has the EVM EEPROM been programmed to your register settings? I'm wondering if at Step 6 you are running the default EEPROM settings that were configured at the factory (refer to the datasheet). In that case, STATUS1, which is routed to D5, shows DPLL Holdover Active mode.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    The EEPROM is indeed programmed to this configuration:

    STATUS0 - DPLL Phase Lock Detection

    STATUS1 - PLL2 Digital Lock Detect

    Thanks,

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 12925 points

    Hi Nir,

    Can you please share your .tcs config that you have used to program the EEPROM?

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    Sorry for the delay, here is the file.10M_REF_32M_OUT7_SE_CMOS.tcs

    Thanks,

    Nir

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    New news? did you run the script?

    Thanks

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 12925 points

    Hi Nir,

    I apologize for the wait. Yes, I ran the script and followed your steps—the same issues are seen on my side. 

    Currently checking with our design team as to why this is the case. I will let you know when we have an update.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    Thanks for your confirmation, waiting for further update.

    Best Regards,

    Nir 

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    Can you please check with the design team regarding my issue?

    Thanks

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 12925 points

    Nir,

    After discussing with design, I have the following updates:

    • The PLLn DLD state is based on the PLLn tuning voltage (Vtune). When the XO input is missing at POR, PLLn DLD may read high because Vtune is falling within the required tuning threshold due to a floating signal or charge pump current leakage. It is not the recommended method for assessing APLL lock. This STATUS signal is meant to be used as a debugging bit.
    • If you are trying to determine DPLL lock, it is recommended to use the LOPL_DPLL or LOFL_DPLL signals instead.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    My intention was to have an indication for:

    1- APLL Lock when using local reference only

    2- DPLL lock when 10MHz reference is valid/active.

    For DPLL lock I do use LOPL_DPLL and it's working just fine

    If APLL DLD is not the recommended method for assessing APLL lock than what would be the right choise?

    Thanks,

    Nir

  • 0 in reply to Nir Alon
    TI__Genius 12925 points

    Nir,

    I understand your ask. For detecting APLL lock to XO when using local reference only, please enable the BAW lock detect and read back R80[7]. Note that this bit cannot be routed to the STATUSx pins.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    My design is a stand alone module (no MCU) so reading the above register is not possible.

    Is there another option?

    Thanks

    Nir 

  • 0 in reply to Nir Alon
    TI__Genius 12925 points

    Hi Nir,

    There is no other status bit besides BAW_LOCK to check APLL lock.

    I need to get more understanding of your application.

    1. Are you looking to check when the APLL is locked in the case that DPLL reference goes away?
    2. In other words, will you have one board (using APLL and DPLL) or two separate boards (one uses the APLL only, the other uses the DPLL + APLL)?
    3. What is the reasoning behind wanting an APLL lock detect bit?

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 600 points

    Hi Jennifer,

    Q1. Yes - the module can indicate APLL locked when high frequency accuracy is not needed, or in case of external reference is malfunction or removed.

    Q2. One board with both APLL & DPLL indicators

    Q3. As describes in Q1.

    Best Regards,

    Nir

  • +1 in reply to Nir Alon
    TI__Genius 12925 points

    Hi Nir,

    You could use the DPLL Holdover Active bit to indicate when the DPLL reference is lost and the device has transitioned into holdover (APLL only mode). Again, this won't indicate if the APLL is locked. The APLL will lock to the XO if there is a valid XO input level and frequency present. You can use the LOS_XO bit to confirm there is an XO input present.


    Regards,

    Jennifer