LMK5B33216EVM: DPLL/APLL Phase lock

Thomas Gayagoy

Part Number: LMK5B33216EVM

Tool/software:

Hello,

We are using a reference input configuration with DPLL3 that seems to uncheck its loss of lock status signals. Measuring the reference input and a relative output, we can't seem to see their phase lock properly. Is there a relation between the DPLL status registers and showing the output/input are phase locked? Is there something we are missing in our configuration that would help with adjusting the frequency/phase of the feedback system to keep the phase locked on the output?

LMK5B_tics_pro_BP_v7.tcs

Thanks,

Tom

11 months ago

0 Jennifer Bernal 11 months ago

TI__Genius 17045 points

Hi Tom,

I assume this is a continuous from the previous thread: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1469348/lmk5b33216evm-dpll3-no-input-selected-lopl-lofl-status-no-holdover.

Were you able to get the DPLL to lock with the configuration I provided in the previous thread? Or does that config also show that the DPLL lock toggles?

Regards,

Jennifer

0 Thomas Gayagoy 11 months ago in reply to Jennifer Bernal

Prodigy 75 points

Hi Jennifer,

What settings do we need to alter to test locking with a 48MHz (SE) input into IN1? Based on your previously posted configuration.

Thanks,
Tom

+1 Jennifer Bernal 11 months ago in reply to Thomas Gayagoy

TI__Genius 17045 points

Hi Tom,

My apologies, the previous config did not factor in IN1. I have modified the config such that the TDC rate is changed to 1MHz so that the DPLL can lock to both 48MHz and 125MHz using the same DPLL FB divider. 1MHz is the GCD of the two input frequencies.

The max TDC rate can be forced in the Start Page:

Please let me know if this helps you:

e2e_LMK5B33216_IN0=125MHz_IN1=48MHz_XO=48MHz.tcs

Regards,

Jennifer

0 Thomas Gayagoy 11 months ago in reply to Jennifer Bernal

Prodigy 75 points

Hi Jennifer,

The new configuration looks like it's locking right away for us with either input. Thank you for the help.

-Tom

0 Jennifer Bernal 11 months ago in reply to Thomas Gayagoy

TI__Genius 17045 points

Hi Thomas,

Glad to hear the config is working for you.

Regards,

Jennifer

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LMK5B33216EVM: DPLL/APLL Phase lock